bfmin

BFloat16 Minimum

BFMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Calculates minimum of BFloat16 elements.

Details

Computes the minimum of BFloat16 (16-bit) elements from two SVE registers under predicate control and stores the result in the destination register. Floating-point exceptions may be generated; condition flags are unaffected. Requires FEAT_SVE_B16B16; AArch64 only.

Pseudocode Operation

for i = 0 to VL/16 - 1
  if Pg[i]
    Zdn[i] ← FP_Min(Zdn[i], Zm[i])
  else
    Zdn[i] ← Zdn[i]

Example

BFMIN z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout

01100101

011

100

Zdn

Format SVE BFloat16

Opcode 0x65078000

Extension FEAT_SVE_B16B16

Operands

Zdn
Dest/Src
Pg
Mask
Zm
Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0xC120A101	BFMIN { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, <Zm>.H	A64	11000001 \| 0 \| 0 \| 10 \| Zm \| 101000 \| 0100 \| 0 \| Zdn \| 1
0xC120A901	BFMIN { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, <Zm>.H	A64	11000001 \| 0 \| 0 \| 10 \| Zm \| 101010 \| 0100 \| 0 \| Zdn \| 0 \| 1
0xC120B101	BFMIN { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H }	A64	11000001 \| 0 \| 0 \| 1 \| Zm \| 0101100 \| 010 \| 0 \| 0 \| Zdn \| 1
0xC120B901	BFMIN { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H }	A64	11000001 \| 0 \| 0 \| 1 \| Zm \| 00101110 \| 010 \| 0 \| 0 \| Zdn \| 0 \| 1
0x65078000	BFMIN <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H	A64	01100101 \| 0 \| 0 \| 00 \| 011 \| 1 \| 100 \| Pg \| Zm \| Zdn

Description

Determine the minimum of active BFloat16 elements of the second source vector and corresponding BFloat16 elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: Inactive elements in the destination vector register remain unmodified. This instruction follows SVE2.1 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV 16;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, 16) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    bits(16) element1 = Elem[operand1, e, 16];
    if ActivePredicateElement(mask, e, 16) then
        bits(16) element2 = Elem[operand2, e, 16];
        Elem[result, e, 16] = BFMin(element1, element2, FPCR);
    else
        Elem[result, e, 16] = element1;

Z[dn, VL] = result;