strex

Store Register Exclusive (Thumb)

STREX <Rd>, <Rt>, [<Rn>]

Stores word if exclusive monitor is open (Thumb).

Details

Attempts to store a 32-bit word from Rt to memory at the address in Rn only if the exclusive monitor is open; writes 0 to Rd if successful, or 1 if the store fails. No condition flags are modified. Execution in Thumb-2 state only; used for atomic operations and compare-and-swap patterns.

Pseudocode Operation

address ← Rn
if ExclusiveMonitor[address] then
  [address] ← Rt
  Rd ← 0
  ClearExclusiveMonitor()
else
  Rd ← 1

Example

STREX r0, r3, [r1]

Encoding

Binary Layout
11101000010
0
Rn
Rt
Rd
imm8
 
Format Thumb Store Excl
Opcode 0xE8400000
Extension A32 (Atomic)

Operands

  • Rd
    Status
  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01800F90 STREX{<c>}{<q>} <Rd>, <Rt>, [<Rn> {, {#}<imm>}] A32 cond | 00011 | 00 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt
0xE8400000 STREX{<c>}{<q>} <Rd>, <Rt>, [<Rn> {, #<imm>}] T32 11101000010 | 0 | Rn | Rt | Rd | imm8

Description

Store Register Exclusive calculates an address from a base register value and an immediate offset, stores a word from a register to the calculated address if the PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n] + imm32;
    if AArch32.ExclusiveMonitorsPass(address,4) then
        MemA[address,4] = R[t];
        R[d] = ZeroExtend('0', 32);
    else
        R[d] = ZeroExtend('1', 32);