fminv

SVE Floating-Point Minimum Reduction

FMINV <Vd>, <Pg>, <Zn>.<T>

Finds min float in vector.

Pseudocode Operation

bits(esize) result = PosInfinity(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element < result (FP) || IsNaN(result) then result = element;
Vd[0 +: esize] ← result;

Example

FMINV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout

01100101

31:24

size

23:22

000

21:19

11

18:17

1

16

001

15:13

Pg

12:10

Zn

9:5

Vd

4:0

 

Format SVE Reduction

Opcode 0x65072000

Extension SVE

Operands

• Vd
  Dest Scalar
• Pg
  Mask
• Zn
  Vector

Related

Other forms of fminv

• fminv Floating-Point Minimum Reduction (NEON)

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0EB0F800	FMINV <V><d>, <Vn>.<T>		A64		0 | Q | 0 | 01110 | 1 | 011000 | 01111 | 10 | Rn | Rd
0x6EB0F800	FMINV S<d>, <Vn>.4S		A64		0 | 1 | 1 | 01110 | 1 | 0 | 11000 | 01111 | 10 | Rn | Rd
0x65072000	FMINV <V><d>, <Pg>, <Zn>.<T>		A64		01100101 | size | 000 | 11 | 1 | 001 | Pg | Zn | Vd

Description

Floating-point minimum horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as +Infinity. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows:

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(esize) identity = FPInfinity('0', esize);

V[d, esize] = FPReducePredicated(ReduceOp_FMIN, operand, mask, identity, FPCR);