ldaex

Load Acquire Exclusive (A32)

LDAEX<c> <Rt>, [<Rn>]

Loads a word with Acquire Exclusive semantics.

Details

Loads a 32-bit word from memory with Acquire Exclusive semantics, allowing subsequent memory operations to observe earlier loads and stores. The processor acquires exclusive access to the address for potential paired store-exclusive. No condition flags are affected. This is an A32-only instruction.

Pseudocode Operation

address ← Rn
MemoryOrder ← Acquire
Rt ← [address]
SET_EXCLUSIVE_MONITOR(address)
DRAIN_ACQUIRE_BARRIER()

Example

LDAEX r3, [r1]

Encoding

Binary Layout
cond
00011
00
1
Rn
Rt
1
1
1
0
1001
1111
 
Format Load/Store
Opcode 0x01900E9F
Extension A32 (Atomic)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01900E9F LDAEX{<c>}{<q>} <Rt>, [<Rn>] A32 cond | 00011 | 00 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111
0xE8D00FEF LDAEX{<c>}{<q>} <Rt>, [<Rn>] T32 11101000110 | 1 | Rn | Rt | 1111 | 1 | 1 | 10 | 1111

Description

Load-Acquire Exclusive Word loads a word from memory, writes it to a register and: The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    AArch32.SetExclusiveMonitors(address, 4);
    R[t] = MemO[address, 4];