extr

Extract (64-bit)

EXTR <Xd>, <Xn>, <Xm>, #<lsb>

Extracts a 64-bit register from a pair.

Details

Extract concatenates two 64-bit registers (high Xn concatenated with low Xm) and extracts a contiguous 64-bit slice starting at bit position lsb. The extracted bits are placed in destination Xd. Condition flags (N, Z, C, V) are unaffected. This is the 64-bit variant with lsb range 0–63.

Pseudocode Operation

temp ← (Xn[63:0] << 64) | Xm[63:0]
Xd ← temp[(lsb + 63):lsb]

Example

EXTR x0, x1, x2, #0

Encoding

Binary Layout
1
00
100111
1
0
Rm
imms
Rn
Rd
 
Format Data Processing
Opcode 0x93C00000
Extension Base

Operands

  • Xd
    Destination 64-bit integer register
  • Xn
    High
  • Xm
    Low
  • lsb
    Least-significant bit position

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x13800000 EXTR <Wd>, <Wn>, <Wm>, #<lsb> A64 0 | 00 | 100111 | 0 | 0 | Rm | imms | Rn | Rd
0x93C00000 EXTR <Xd>, <Xn>, <Xm>, #<lsb> A64 1 | 00 | 100111 | 1 | 0 | Rm | imms | Rn | Rd

Description

Extract register extracts a register from a pair of registers.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = X[m, datasize];
bits(2*datasize) concat = operand1:operand2;

result = concat<(lsb+datasize)-1:lsb>;

X[d, datasize] = result;