extr

Extract (64-bit)

EXTR <Xd>, <Xn>, <Xm>, #<lsb>

Extracts a 64-bit register from a pair.

Pseudocode Operation

temp ← (Xn[63:0] << 64) | Xm[63:0]
Xd ← temp[(lsb + 63):lsb]

Example

EXTR x0, x1, x2, #0

Encoding

Binary Layout

1

31

00

30:29

100111

28:23

1

22

0

21

Rm

20:16

imms

15:10

Rn

9:5

Rd

4:0

 

Format Data Processing

Opcode 0x93C00000

Extension Base

Operands

• Xd
  Destination 64-bit integer register
• Xn
  High
• Xm
  Low
• lsb
  Least-significant bit position

Related

Other forms of extr

• extr Extract

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x13800000	EXTR <Wd>, <Wn>, <Wm>, #<lsb>		A64		0 | 00 | 100111 | 0 | 0 | Rm | imms | Rn | Rd
0x93C00000	EXTR <Xd>, <Xn>, <Xm>, #<lsb>		A64		1 | 00 | 100111 | 1 | 0 | Rm | imms | Rn | Rd

Description

Extract register extracts a register from a pair of registers.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = X[m, datasize];
bits(2*datasize) concat = operand1:operand2;

result = concat<(lsb+datasize)-1:lsb>;

X[d, datasize] = result;