vshrn

Vector Shift Right Narrow

VSHRN<c>.<dt> <Dd>, <Qm>, #<imm>

Shifts right and narrows result.

Details

Shifts each element in the 128-bit source register right by an immediate number of bits, narrows the result to half-width, and stores the narrowed values in the 64-bit destination register. For example, 16-bit results from 32-bit elements are stored in a 64-bit destination. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension.

Pseudocode Operation

shift_amount ← DecodeImmShift(imm6, input_element_size)
output_element_size ← input_element_size / 2
for i = 0 to 63 by output_element_size:
  element ← Qm[i*2+input_element_size*2-1:i*2]
  shifted ← element >> shift_amount
  Dd[i+output_element_size-1:i] ← shifted[output_element_size-1:0]

Example

VSHRN.dt d0, q2, #16

Encoding

Binary Layout
1111001
0
1
D
imm6
Vd
1000
0
0
M
1
Vm
 
Format NEON Shift
Opcode 0xF2800810
Extension NEON (SIMD)

Operands

  • Dd
    Dest Narrow
  • Qm
    Src Wide
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800810 VSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm> A32 1111001 | 0 | 1 | D | imm6 | Vd | 1000 | 0 | 0 | M | 1 | Vm
0xEF800810 VSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm> T32 111 | 0 | 11111 | D | imm6 | Vd | 1000 | 0 | 0 | M | 1 | Vm
0xF3B20200 VSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 A32 111100111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm
0xFFB20200 VSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 T32 111111111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm

Description

Vector Shift Right Narrow takes each element in a vector, right shifts them by an immediate value, and places the truncated results in the destination vector. For rounded results, see VRSHRN. The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. The destination elements are half the size of the source elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        result = LSR(Elem[Qin[m>>1],e,2*esize], shift_amount);
        Elem[D[d],e,esize] = result<esize-1:0>;