crc32cb

CRC32C Byte

CRC32CB <Wd>, <Wn>, <Wm>

Updates CRC32C (Castagnoli) checksum with a byte.

Details

Updates a 32-bit CRC32C (Castagnoli) checksum by processing an 8-bit (byte) value from the data register. The instruction computes the CRC32C polynomial remainder (iSCSI polynomial) and stores the result in the destination register. No condition flags are affected; this instruction requires the CRC extension and executes only in AArch64.

Pseudocode Operation

Wd ← CRC32CPolynomial(Wn, Wm<7:0>)

Example

CRC32CB w0, w1, w2

Encoding

Binary Layout
0
0
0
11010110
Rm
010
1
00
Rn
Rd
 
Format Data Processing
Opcode 0x1AC05000
Extension CRC

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    Acc
  • Wm
    Data

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1AC05000 CRC32CB <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 010 | 1 | 00 | Rn | Rd

Description

CRC32C checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation. In an Armv8.0 implementation, this is an OPTIONAL instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.

Operation

bits(32) acc = X[n, 32];    // accumulator
bits(size) val = X[m, size];    // input value
bits(32) poly = 0x1EDC6F41<31:0>;

bits(32+size) tempacc = BitReverse(acc):Zeros(size);
bits(size+32) tempval = BitReverse(val):Zeros(32);

// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
X[d, 32] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));