stlexd

Store Release Exclusive Double (A32)

STLEXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>]

Stores a doubleword with Release semantics if exclusive.

Details

Stores a doubleword (64-bit value) to memory with Release semantics if the exclusive monitor is set for the address. The value is loaded from the register pair [Rt, Rt2], and a status is written to Rd (0=success, 1=failure). This is an exclusive store with full Release memory ordering. No condition flags are affected. Execution state: A32 only; Rt must be even-numbered and Rt2=Rt+1.

Pseudocode Operation

if ExclusiveMonitorsPass(address=Rn, size=8) then
  [Rn] ← Rt
  [Rn+4] ← Rt2
  Rd ← 0
  ClearExclusiveMonitors()
else
  Rd ← 1

Example

STLEXD r0, r3, r4, [r1]

Encoding

Binary Layout
cond
00011
01
0
Rn
Rd
1
1
1
0
1001
Rt
 
Format Store Excl
Opcode 0x01A00E90
Extension A32 (Atomic)

Operands

  • Rd
    Status
  • Rt
    Transfer general-purpose register (load/store)
  • Rt2
    Second transfer register (load/store pair)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01A00E90 STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>] A32 cond | 00011 | 01 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt
0xE8C000F0 STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>] T32 11101000110 | 0 | Rn | Rt | Rt2 | 1 | 1 | 11 | Rd

Description

Store-Release Exclusive Doubleword stores a doubleword from two registers to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4.
    value = if BigEndian(AccessType_GPR) then R[t]:R[t2] else R[t2]:R[t];
    if AArch32.ExclusiveMonitorsPass(address, 8) then
        MemO[address, 8] = value;
        R[d] = ZeroExtend('0', 32);
    else
        R[d] = ZeroExtend('1', 32);