usdot

Unsigned-Signed Dot Product (NEON)

USDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Dot product of Unsigned Int8 and Signed Int8.

Details

Performs an unsigned-signed 8-bit integer dot product, multiplying unsigned Int8 elements from Vn with signed Int8 elements from Vm and accumulating into 32-bit integer lanes of Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM architectural feature. No condition flags are affected; this is an AArch64-only instruction.

Pseudocode Operation

for e = 0 to (128 / 32) - 1
  Vd[e] ← Vd[e] + (uint(Vn[4×e]) × sint(Vm[4×e]) +
                   uint(Vn[4×e+1]) × sint(Vm[4×e+1]) +
                   uint(Vn[4×e+2]) × sint(Vm[4×e+2]) +
                   uint(Vn[4×e+3]) × sint(Vm[4×e+3]))
  // Each Vd[e] is a 32-bit signed result

Example

USDOT v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
10
0
Rm
1
0011
1
Rn
Rd
 
Format NEON 3-Reg
Opcode 0x0E809C00
Extension FEAT_I8MM (AI)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    Unsigned
  • Vm
    Signed

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F80F000 USDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] A64 0 | Q | 0 | 01111 | 1 | 0 | L | M | Rm | 1111 | H | 0 | Rn | Rd
0x0E809C00 USDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 0 | 01110 | 10 | 0 | Rm | 1 | 0011 | 1 | Rn | Rd
0x44807800 USDOT <Zda>.S, <Zn>.B, <Zm>.B A64 01000100 | 1 | 0 | 0 | Zm | 011110 | Zn | Zda
0x44A01800 USDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] A64 01000100 | 1 | 0 | 1 | i2 | Zm | 00011 | 0 | Zn | Zda
0xC1501028 USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 1 | 0 | 1 | off3
0xC1509028 USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] A64 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 1 | 0 | 1 | off3
0xC1201408 USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B A64 11 | 0000010010 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3
0xC1301408 USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B A64 11 | 0000010011 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3
0xC1A01408 USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } A64 11 | 000001101 | Zm | 00 | Rv | 101 | Zn | 00 | 1 | off3
0xC1A11408 USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } A64 11 | 000001101 | Zm | 010 | Rv | 101 | Zn | 000 | 1 | off3

Description

Dot Product vector form with unsigned and signed integers. This instruction performs the dot product of the four unsigned 8-bit integer values in each 32-bit element of the first source register with the four signed 8-bit integer values in the corresponding 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) operand3 = V[d, datasize];
bits(datasize) result;

for e = 0 to elements-1
    bits(32) res = Elem[operand3, e, 32];
    for b = 0 to 3
        integer element1 = UInt(Elem[operand1, 4*e+b, 8]);
        integer element2 = SInt(Elem[operand2, 4*e+b, 8]);
        res = res + element1 * element2;
    Elem[result, e, 32] = res;

V[d, datasize] = result;