sm3tt1b

SM3 Step 2B (A32)

SM3TT1B.32 <Qd>, <Dn>, <Dm>, #<imm>

SM3 cryptographic hash step 2B.

Pseudocode Operation

rot ← imm * 8
Qd ← SM3_TT1B(Dn, Dm, rot)

Example

SM3TT1B.32 q0, d1, d2, #16

Encoding

Binary Layout

11001110010

31:21

20:16

15:14

imm2

13:12

11:10

9:5

4:0

Format Crypto Imm

Opcode 0xCE408400

Extension Crypto (SM3)

Operands

Qd
Destination 128-bit SIMD register
Dn
First source 64-bit SIMD/FP register
Dm
Second source 64-bit SIMD/FP register
imm
Rot

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xCE408400	SM3TT1B <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]		A64		11001110010 \| Rm \| 10 \| imm2 \| 01 \| Rn \| Rd

Description

SM3TT1B takes three 128-bit vectors from three source SIMD&FP registers and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a 32-bit majority function between the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values: The result of this addition is returned as the top element of the result. The other elements of the result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 9. This instruction is implemented only when FEAT_SM3 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vm = V[m, 128];
bits(128) Vn = V[n, 128];
bits(128) Vd = V[d, 128];
bits(32) WjPrime;
bits(128) result;
bits(32) TT1;
bits(32) SS2;

WjPrime = Elem[Vm, i, 32];
SS2 = Vn<127:96> EOR ROL(Vd<127:96>, 12);
TT1 = (Vd<127:96> AND Vd<63:32>) OR (Vd<127:96> AND Vd<95:64>) OR (Vd<63:32> AND Vd<95:64>);
TT1 = (TT1+Vd<31:0>+SS2+WjPrime)<31:0>;
result<31:0> = Vd<63:32>;
result<63:32> = ROL(Vd<95:64>, 9);
result<95:64> = Vd<127:96>;
result<127:96> = TT1;
V[d, 128] = result;