sm3tt1b
SM3 Step 2B (A32)
SM3TT1B.32 <Qd>, <Dn>, <Dm>, #<imm>
SM3 cryptographic hash step 2B.
Details
The SM3 Step 2B instruction sM3 cryptographic hash step 2B.
Pseudocode Operation
// SM3 cryptographic hash step 2B
Example
SM3TT1B.32 q0, d1, d2, #16
Encoding
Binary Layout
11111110
10
imm2
Vn
Vd
1000
N
Q
M
1
Vm
Operands
-
Qd
Destination 128-bit SIMD register -
Dn
First source 64-bit SIMD/FP register -
Dm
Second source 64-bit SIMD/FP register -
imm
Rot