not

Vector Bitwise NOT

NOT <Vd>.<T>, <Vn>.<T>

Inverts all bits. (Alias for MVN).

Details

Performs a bitwise NOT operation (one's complement) on each bit of the source vector, placing the inverted result in the destination vector. This instruction is an alias for MVN in NEON and operates on all vector element sizes. No condition flags are affected. Available in AArch64 NEON for both 64-bit and 128-bit vectors.

Pseudocode Operation

for i = 0 to bits_in_vector - 1:
  Vd[i] ← NOT Vn[i]

Example

NOT v0.4s.T, v1.4s.T

Encoding

Binary Layout
0
Q
1
01110
00
10000
00101
10
Rn
Rd
 
Format SIMD Two Register
Opcode 0x2E205800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E205800 NOT <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 00 | 10000 | 00101 | 10 | Rn | Rd
0x25004200 NOT <Pd>.B, <Pg>/Z, <Pn>.B A64 00100101 | 0 | 0 | 00 | Pm | 01 | Pg | 1 | Pn | 0 | Pd
0x041EA000 NOT <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 00000100 | size | 011 | 11 | 0 | 101 | Pg | Zn | Zd

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) result;
bits(esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = NOT(element);

V[d, datasize] = result;