vmovl

Vector Move Long

VMOVL<c>.<dt> <Qd>, <Dm>

Copies N-bit elements to 2N-bit elements (Widening).

Pseudocode Operation

for i = 0 to (64 / source_element_width) - 1:
  Qd[i] ← ZeroExtend(Dm[i]) or SignExtend(Dm[i])

Example

VMOVL.dt q0, d2

Encoding

Binary Layout

1111001

31:25

U

24

1

23

D

22

imm3H

21:19

000

18:16

Vd

15:12

1010

11:8

0

7

0

6

M

5

1

4

Vm

3:0

 

Format NEON 2-Reg

Opcode 0xF2800A10

Extension NEON (SIMD)

Operands

• Qd
  Dest Wide
• Dm
  Src Narrow

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2800A10	VMOVL{<c>}{<q>}.<dt> <Qd>, <Dm>		A32		1111001 | U | 1 | D | imm3H | 000 | Vd | 1010 | 0 | 0 | M | 1 | Vm
0xEF800A10	VMOVL{<c>}{<q>}.<dt> <Qd>, <Dm>		T32		111 | U | 11111 | D | imm3H | 000 | Vd | 1010 | 0 | 0 | M | 1 | Vm

Description

Vector Move Long takes each element in a doubleword vector, sign or zero-extends them to twice their original length, and places the results in a quadword vector. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        result = Int(Elem[Din[m],e,esize], unsigned);
        Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;