vmovl

Vector Move Long

VMOVL<c>.<dt> <Qd>, <Dm>

Copies N-bit elements to 2N-bit elements (Widening).

Details

Widens N-bit elements from a 64-bit source register to 2N-bit elements in a 128-bit destination register, with zero or sign extension based on the data type. The Q field and element size encoding determine which half of the source to use and the widening operation. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to (64 / source_element_width) - 1:
  Qd[i] ← ZeroExtend(Dm[i]) or SignExtend(Dm[i])

Example

VMOVL.dt q0, d2

Encoding

Binary Layout
1111001
U
1
D
imm3H
000
Vd
1010
0
0
M
1
Vm
 
Format NEON 2-Reg
Opcode 0xF2800A10
Extension NEON (SIMD)

Operands

  • Qd
    Dest Wide
  • Dm
    Src Narrow

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800A10 VMOVL{<c>}{<q>}.<dt> <Qd>, <Dm> A32 1111001 | U | 1 | D | imm3H | 000 | Vd | 1010 | 0 | 0 | M | 1 | Vm
0xEF800A10 VMOVL{<c>}{<q>}.<dt> <Qd>, <Dm> T32 111 | U | 11111 | D | imm3H | 000 | Vd | 1010 | 0 | 0 | M | 1 | Vm

Description

Vector Move Long takes each element in a doubleword vector, sign or zero-extends them to twice their original length, and places the results in a quadword vector. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        result = Int(Elem[Din[m],e,esize], unsigned);
        Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;