csinc

Conditional Select Increment

CSINC <Wd>, <Wn>, <Wm>, <cond>

Selects Wn if cond true, else (Wm + 1).

Pseudocode Operation

if ConditionHolds(cond) then
  Wd ← Wn
else
  Wd ← Wm + 1

Example

CSINC w0, w1, w2, cond

Encoding

Binary Layout
0
31
0
30
0
29
11010100
28:21
Rm
20:16
cond
15:12
0
11
1
10
Rn
9:5
Rd
4:0
 
Format Cond Select
Opcode 0x1A800400
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    True Src
  • Wm
    False Src
  • cond
    Cond

Related

Across architectures

Conditional Select (Branchless Move) : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1A800400 CSINC <Wd>, <Wn>, <Wm>, <cond> A64 0 | 0 | 0 | 11010100 | Rm | cond | 0 | 1 | Rn | Rd
0x9A800400 CSINC <Xd>, <Xn>, <Xm>, <cond> A64 1 | 0 | 0 | 11010100 | Rm | cond | 0 | 1 | Rn | Rd

Description

Conditional Select Increment returns, in the destination register, the value of the first source register if the condition is TRUE, and otherwise returns the value of the second source register incremented by 1.

Operation

bits(datasize) result;
if ConditionHolds(cond) then
    result = X[n, datasize];
else
    result = X[m, datasize];
    result = result + 1;

X[d, datasize] = result;