stlexb

Store Release Exclusive Byte (A32)

STLEXB<c> <Rd>, <Rt>, [<Rn>]

Stores a byte with Release semantics if exclusive.

Details

Attempts to store a byte to memory at the address in Rn with Release semantics if the location is marked exclusive. The result of the store attempt (0 for success, 1 for failure) is written to Rd. Release semantics ensure that preceding memory operations are not reordered after this store. No condition flags are affected.

Pseudocode Operation

if ExclusiveLocal then [Rn] ← Rt[7:0]; Rd ← 0; Release(); ExclusiveLocal ← FALSE else Rd ← 1 endif

Example

STLEXB r0, r3, [r1]

Encoding

Binary Layout
cond
00011
10
0
Rn
Rd
1
1
1
0
1001
Rt
 
Format Store Excl
Opcode 0x01C00E90
Extension A32 (Atomic)

Operands

  • Rd
    Status
  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01C00E90 STLEXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] A32 cond | 00011 | 10 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt
0xE8C00FC0 STLEXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] T32 11101000110 | 0 | Rn | Rt | 1111 | 1 | 1 | 00 | Rd

Description

Store-Release Exclusive Byte stores a byte from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    if AArch32.ExclusiveMonitorsPass(address,1) then
        MemO[address, 1] = R[t]<7:0>;
        R[d] = ZeroExtend('0', 32);
    else
        R[d] = ZeroExtend('1', 32);