vqshl

Vector Saturating Shift Left (Register)

VQSHL<c>.<dt> <Qd>, <Qm>, <Qn>

Shifts left with saturation based on register.

Pseudocode Operation

for i = 0 to elements-1 do
  shift_amount ← SignExtend(Qn[i])
  if shift_amount >= 0 then
    result ← SatQ(Qm[i] << shift_amount, esize)
  else
    result ← SatQ(Qm[i] >> (-shift_amount), esize)
  Qd[i] ← result

Example

VQSHL.dt q0, q2, q1

Encoding

Binary Layout

1111001

31:25

U

24

0

23

D

22

size

21:20

Vn

19:16

Vd

15:12

0100

11:8

N

7

1

6

M

5

1

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF2000450

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register
• Qn
  Shift Reg

Related

Other forms of vqshl

• vqshl Vector Saturating Shift Left (Immediate)

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2800710	VQSHL{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 011 | 1 | L | 0 | M | 1 | Vm
0xF2800750	VQSHL{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 011 | 1 | L | 1 | M | 1 | Vm
0xEF800710	VQSHL{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 011 | 1 | L | 0 | M | 1 | Vm
0xEF800750	VQSHL{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 011 | 1 | L | 1 | M | 1 | Vm
0xF2000410	VQSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn>		A32		1111001 | U | 0 | D | size | Vn | Vd | 0100 | N | 0 | M | 1 | Vm
0xF2000450	VQSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn>		A32		1111001 | U | 0 | D | size | Vn | Vd | 0100 | N | 1 | M | 1 | Vm
0xEF000410	VQSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn>		T32		111 | U | 11110 | D | size | Vn | Vd | 0100 | N | 0 | M | 1 | Vm
0xEF000450	VQSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn>		T32		111 | U | 11110 | D | size | Vn | Vd | 0100 | N | 1 | M | 1 | Vm

Description

Vector Saturating Shift Left (register) takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are truncated. For rounded results, see VQRSHL. The first operand and result elements are the same data type, and can be any one of: The second operand is a signed integer of the same size. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            shift = SInt(Elem[D[n+r],e,esize]<7:0>);
            operand = Int(Elem[D[m+r],e,esize], unsigned);
            boolean sat;
            bits(esize) result;
            if shift >= 0 then
                (result,sat) = SatQ(operand << shift, esize, unsigned);
            else
                (result,sat) = SatQ(operand >> -shift, esize, unsigned);
            Elem[D[d+r],e,esize] = result;
            if sat then FPSCR.QC = '1';