NEON (SIMD) Instructions

211 ARM instructions in this extension - showing 100 per page, page 1 of 3 - click any row for encoding, pseudocode, and full documentation.

Mnemonic ⇅ Syntax Format ⇅ Summary
abs ABS <Vd>.<T>, <Vn>.<T> SIMD Two Register Calculates absolute value of integer elements.
add ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Adds corresponding elements in two vectors.
addp ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Adds adjacent pairs of elements.
addv ADDV <V><d>, <Vn>.<T> SIMD Across Lane Adds all elements of the vector into a scalar result.
and AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Bitwise AND of two vectors.
bic BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register ANDs Vd with NOT of Vm.
bif BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Inserts bits from Vn into Vd where Vm (mask) is 0.
bit BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Inserts bits from Vn into Vd where Vm (mask) is 1.
bsl BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Selects bits from Vn or Vm based on Vd (mask). (Vd = (Vd & Vn) | (~Vd & Vm)).
clz CLZ <Vd>.<T>, <Vn>.<T> SIMD Two Register Counts leading zeros for each element.
cmeq CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Compares elements (Vn == Vm) and sets bits to all 1s or 0s.
cmge CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Compares elements (Vn >= Vm).
cmgt CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Compares elements (Vn > Vm) and sets bits to all 1s or 0s.
cmtst CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Tests if any bits match ((Vn & Vm) != 0).
cnt CNT <Vd>.<T>, <Vn>.<T> SIMD Two Register Counts set bits (population count) per byte.
dup DUP <Vd>.<T>, <R><n> SIMD Copy Duplicates a general-purpose register to all vector elements.
dup DUP <Vd>.<T>, <Vn>.<Ts>[<index>] SIMD Copy Duplicates a vector element to all elements in destination.
eor EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Bitwise XOR of two vectors.
ext EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index> SIMD Extract Extracts a vector from a pair of vectors (Sliding window).
fabs FABS <Vd>.<T>, <Vn>.<T> SIMD Two Register Calculates absolute value for each element.
fadd FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Adds elements of two floating-point vectors.
faddp FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Adds adjacent pairs of float elements.
fcvtl FCVTL <Vd>.<Td>, <Vn>.<Ts> SIMD Two Register Converts narrow floats to wide floats (e.g., Half -> Single).
fcvtn FCVTN <Vd>.<Td>, <Vn>.<Ts> SIMD Two Register Converts wide floats to narrow floats (e.g., Single -> Half).
fcvtzs FCVTZS <Vd>.<T>, <Vn>.<T> {, #<fbits>} SIMD Two Register Converts floats to signed integers (Truncate).
fcvtzu FCVTZU <Vd>.<T>, <Vn>.<T> {, #<fbits>} SIMD Two Register Converts floats to unsigned integers (Truncate).
fdiv FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Divides elements of floating-point vectors.
fmax FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Compares and returns the larger value per element.
fmaxp FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Max of adjacent float elements.
fmin FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Compares and returns the smaller value per element.
fminp FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Min of adjacent float elements.
fmla FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Multiplies and adds to destination (Vd = Vd + Vn * Vm).
fmls FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Multiplies and subtracts from destination (Vd = Vd - Vn * Vm).
fmul FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Multiplies elements of floating-point vectors.
fneg FNEG <Vd>.<T>, <Vn>.<T> SIMD Two Register Negates each element.
frecpe FRECPE <Vd>.<T>, <Vn>.<T> SIMD Two Register Estimates reciprocal (1/x) for floats.
frecps FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Newton-Raphson step for reciprocal refinement.
frsqrte FRSQRTE <Vd>.<T>, <Vn>.<T> SIMD Two Register Estimates reciprocal square root (1/sqrt(x)).
frsqrts FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Newton-Raphson step for reciprocal square root refinement.
fsqrt FSQRT <Vd>.<T>, <Vn>.<T> SIMD Two Register Calculates square root for each element.
fsub FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Subtracts elements of floating-point vectors.
ins INS <Vd>.<Ts>[<index>], <Rn> SIMD Copy Moves data from a GPR to a specific vector element.
ld1 LD1 { <Vt>.<T>, ... }, [<Xn|SP>] SIMD Load/Store Loads one element structure from memory into 1-4 registers.
ld1r LD1R { <Vt>.<T> }, [<Xn|SP>] SIMD Load/Store Loads one element and replicates it to all lanes of the vector.
ld2 LD2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] SIMD Load/Store Loads two-element structures from memory into two registers (De-interleave).
ld2r LD2R { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] SIMD Load/Store Loads 2 elements and replicates them to all lanes.
ld3 LD3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] SIMD Load/Store Loads three-element structures (e.g., RGB) into three registers.
ld4 LD4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] SIMD Load/Store Loads four-element structures (e.g., RGBA) into four registers.
mla MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Multiplies elements and adds to destination (Vd = Vd + Vn * Vm).
mls MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Multiplies elements and subtracts from destination (Vd = Vd - Vn * Vm).
mov MOV <Vd>.<T>, <Vn>.<T> SIMD Alias Copies a vector register (Alias for ORR Vd, Vn, Vn).
mov MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>] SIMD Copy Moves a vector element to another vector element (Alias for INS).
movi MOVI <Vd>.<T>, #<imm8> {, lsl #<shift>} SIMD Modified Imm Moves an immediate value into every element of a vector.
mul MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Multiplies corresponding elements in two vectors.
mvn MVN <Vd>.<T>, <Vn>.<T> SIMD Two Register Bitwise NOT of a vector.
mvni MVNI <Vd>.<T>, #<imm8> {, lsl #<shift>} SIMD Modified Imm Moves the inverse of an immediate value into every element.
neg NEG <Vd>.<T>, <Vn>.<T> SIMD Two Register Negates integer elements.
not NOT <Vd>.<T>, <Vn>.<T> SIMD Two Register Inverts all bits. (Alias for MVN).
orn ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register ORs Vd with NOT of Vm.
orr ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Bitwise OR of two vectors.
pmul PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Performs polynomial multiplication over {0,1}.
saddl SADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Adds lower/upper halves of signed vectors, producing wider result (Widening).
saddw SADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> SIMD Three Register Diff Adds a wide vector to the lower/upper half of a narrow vector.
shl SHL <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Shifts elements left by immediate value.
shll SHLL <Vd>.<Td>, <Vn>.<Ts>, #<shift> SIMD Shift Imm Shifts narrow vector left, extending to wide result.
shrn SHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift> SIMD Shift Imm Shifts wide vector right, narrowing to destination (Upper/Lower).
sli SLI <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Shifts source left and inserts into destination.
smax SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Returns larger signed integer per element.
smaxv SMAXV <V><d>, <Vn>.<T> SIMD Across Lane Finds the maximum signed value across the vector.
smin SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Returns smaller signed integer per element.
smlal SMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Multiplies signed narrow vectors and adds to wide destination.
smull SMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Multiplies signed narrow vectors, producing wider result.
sqadd SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Adds signed integers with saturation.
sqsub SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Subtracts signed integers with saturation.
sqxtn SQXTN <Vd>.<Tb>, <Vn>.<Ta> SIMD Shift Imm Reads wide elements, saturates, and narrows.
sri SRI <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Shifts source right and inserts into destination.
sshr SSHR <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Shifts elements right (arithmetic/sign-extending).
ssra SSRA <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Arithmetic right shift and add to destination.
ssubl SSUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Subtracts signed narrow vectors, producing wider result.
st1 ST1 { <Vt>.<T>, ... }, [<Xn|SP>] SIMD Load/Store Stores one element structure from 1-4 registers to memory.
st2 ST2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] SIMD Load/Store Stores two-element structures from two registers to memory (Interleave).
st3 ST3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] SIMD Load/Store Stores three-element structures from three registers (Interleave RGB).
st4 ST4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] SIMD Load/Store Stores four-element structures from four registers (Interleave RGBA).
sub SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Subtracts elements of Vm from Vn.
tbl TBL <Vd>.<T>, { <Vn>.16B, ... }, <Vm>.<T> SIMD Table Look up elements in a table of vectors using indices.
trn1 TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Transposes elements (Lower).
trn2 TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Transposes elements (Upper).
uaddl UADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Adds lower/upper halves of unsigned vectors, producing wider result.
uaddw UADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> SIMD Three Register Diff Adds a wide vector to the lower/upper half of a narrow vector (Unsigned).
umax UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Returns larger unsigned integer per element.
umin UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Returns smaller unsigned integer per element.
uminv UMINV <V><d>, <Vn>.<T> SIMD Across Lane Finds the minimum unsigned value across the vector.
umlal UMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Multiplies unsigned narrow vectors and adds to wide destination.
umull UMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Multiplies unsigned narrow vectors, producing wider result.
uqadd UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Adds unsigned integers with saturation.
uqsub UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Subtracts unsigned integers with saturation.
uqxtn UQXTN <Vd>.<Tb>, <Vn>.<Ta> SIMD Shift Imm Reads wide unsigned elements, saturates, and narrows.
urecpe URECPE <Vd>.<T>, <Vn>.<T> SIMD Two Register Estimates reciprocal for unsigned integers.
ushr USHR <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Shifts elements right (logical).
usra USRA <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Logical right shift and add to destination.