NEON (SIMD) Instructions
211 ARM instructions in this extension - showing 100 per page, page 2 of 3 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| usubl | USUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> | SIMD Three Register Diff | Subtracts unsigned narrow vectors, producing wider result. |
| uzp1 | UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | De-interleaves lower halves (Selects odd elements). |
| uzp2 | UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Permute | De-interleaves upper halves (Selects even elements). |
| vaba | VABA<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Computes absolute difference and adds to accumulator. |
| vabal | VABAL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | Computes absolute difference of narrow elements and adds to wide acc. |
| vabd | VABD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Computes absolute difference between elements. |
| vabdl | VABDL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | Computes absolute difference of narrow elements to wide result. |
| vabs | VABS<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Calculates absolute value of integer/float elements. |
| vacge | VACGE<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | Compares absolute values (|Vn| >= |Vm|). |
| vacgt | VACGT<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | Compares absolute values (|Vn| > |Vm|). |
| vadd | VADD<c>.I<size> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Adds integer elements of two vectors. |
| vaddhn | VADDHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | Adds 2N-bit elements, selects high N-bits for result. |
| vaddl | VADDL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | Adds N-bit elements, producing 2N-bit results. |
| vaddw | VADDW<c>.<dt> <Qd>, <Qn>, <Dm> | NEON 3-Reg | Adds N-bit vector to 2N-bit vector. |
| vand | VAND<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Bitwise AND of two vectors. |
| vbic | VBIC<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | ANDs Vd with NOT of Vm (Vd & ~Vm). |
| vbif | VBIF<c> <Qd>, <Qm>, <Qn> | NEON 3-Reg | Inserts bits from Vm into Vd where Vn (mask) is 0. |
| vbit | VBIT<c> <Qd>, <Qm>, <Qn> | NEON 3-Reg | Inserts bits from Vm into Vd where Vn (mask) is 1. |
| vbsl | VBSL<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Selects bits from Vn or Vm based on Vd (mask). |
| vceq | VCEQ<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Sets destination bits to all 1s if elements equal, else 0s. |
| vcge | VCGE<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Compares elements (>=) and sets result mask. |
| vcgt | VCGT<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Compares elements (>) and sets result mask. |
| vcle | VCLE<c>.<dt> <Qd>, <Qn>, <Qm> | NEON Alias | Compares elements (<=). Alias for VCGE with swapped operands. |
| vcls | VCLS<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Counts number of consecutive sign bits. |
| vclt | VCLT<c>.<dt> <Qd>, <Qn>, <Qm> | NEON Alias | Compares elements (<). Alias for VCGT with swapped operands. |
| vclz | VCLZ<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Counts number of consecutive zeros. |
| vcnt | VCNT<c>.8 <Qd>, <Qm> | NEON 2-Reg | Population count (number of 1s) per byte. |
| vcvta | VCVTA<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | Converts float to integer, rounding to nearest. |
| vcvtm | VCVTM<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | Converts float to integer, rounding towards -Inf (Floor). |
| vcvtn | VCVTN<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | Converts float to integer, rounding to nearest even. |
| vcvtp | VCVTP<c>.<dt>.F32 <Qd>, <Qm> | NEON 2-Reg | Converts float to integer, rounding towards +Inf (Ceil). |
| vdup | VDUP<c>.<dt> <Qd>, <Dm[x]> | NEON Scalar | Duplicates a scalar value to all lanes of a vector. |
| veor | VEOR<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Bitwise XOR of two vectors. |
| vext | VEXT<c>.8 <Qd>, <Qn>, <Qm>, #<imm> | NEON Extract | Extracts a new vector from a pair of vectors (Sliding window). |
| vhadd | VHADD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Add elements and shift right by 1 (Average). |
| vhsub | VHSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Subtract elements and shift right by 1. |
| vld1 | VLD1<c>.<size> <list>, [<Rn>]{!} | NEON Load | Loads vector data from memory (interleaved or sequential). |
| vld2 | VLD2<c>.<size> <list>, [<Rn>]{!} | NEON Load | De-interleaves 2 streams of data while loading. |
| vld3 | VLD3<c>.<size> <list>, [<Rn>]{!} | NEON Load | Loads three-element structures (e.g., RGB) and de-interleaves them into three registers. |
| vld4 | VLD4<c>.<size> <list>, [<Rn>]{!} | NEON Load | Loads four-element structures (e.g., RGBA) and de-interleaves them into four registers. |
| vmax | VMAX<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Selects maximum value from elements. |
| vmaxnm | VMAXNM<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | Returns larger value, handling NaNs per IEEE 754-2008. |
| vmin | VMIN<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Selects minimum value from elements. |
| vminnm | VMINNM<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | Returns smaller value, handling NaNs per IEEE 754-2008. |
| vmla | VMLA<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Multiplies and adds to accumulator. |
| vmls | VMLS<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Multiplies and subtracts from accumulator. |
| vmov | VMOV<c>.<dt> <Qd>, #<imm> | NEON Imm | Moves immediate value into vector. |
| vmovl | VMOVL<c>.<dt> <Qd>, <Dm> | NEON 2-Reg | Copies N-bit elements to 2N-bit elements (Widening). |
| vmovn | VMOVN<c>.<dt> <Dd>, <Qm> | NEON 2-Reg | Copies 2N-bit elements to N-bit elements (Narrowing). |
| vmul | VMUL<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Multiplies elements. |
| vmull | VMULL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | Multiplies N-bit elements producing 2N-bit results. |
| vmvn | VMVN<c> <Qd>, <Qm> | NEON 2-Reg | Moves bitwise inverse of immediate/register. |
| vneg | VNEG<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Negates integer/float elements. |
| vorn | VORN<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Bitwise OR with NOT (Vd = Vn | ~Vm). |
| vorr | VORR<c> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Bitwise OR of two vectors. |
| vpadal | VPADAL<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Adds adjacent pairs and accumulates into wide destination. |
| vpadd | VPADD<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | Adds adjacent pairs of elements. |
| vpaddl | VPADDL<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Adds adjacent pairs and produces wide result. |
| vpmax | VPMAX<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | Maximum of adjacent pairs. |
| vpmin | VPMIN<c>.<dt> <Dd>, <Dn>, <Dm> | NEON 3-Reg | Minimum of adjacent pairs. |
| vqadd | VQADD<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Adds elements with saturation. |
| vqdmlal | VQDMLAL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | Multiplies, doubles, saturates, and adds to accumulator (High precision DSP). |
| vqdmlsl | VQDMLSL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | Multiplies, doubles, saturates, and subtracts from accumulator. |
| vqdmulh | VQDMULH<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Multiplies, doubles, saturates, and keeps high half. |
| vqdmull | VQDMULL<c>.<dt> <Qd>, <Dn>, <Dm> | NEON 3-Reg | Multiplies narrow elements, doubles, and saturates into wide elements. |
| vqrdmulh | VQRDMULH<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Fixed-point multiply with rounding and saturation. |
| vqrshl | VQRSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | Shifts left with saturation and rounding. |
| vqrshrn | VQRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | Shifts right, saturates, rounds, and narrows. |
| vqshl | VQSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | Shifts left with saturation based on register. |
| vqshl | VQSHL<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts left with saturation based on immediate. |
| vqshlu | VQSHLU<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts signed elements left, saturating to unsigned result. |
| vqshr | VQSHR<c>.U<size> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts right with saturation (Unsigned). |
| vqshrn | VQSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | Shifts right, saturates, and narrows. |
| vqsub | VQSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Subtracts elements with saturation. |
| vraddhn | VRADDHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | Adds wide elements, rounds, and returns high narrow half. |
| vrecpe | VRECPE<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Estimates reciprocal (1/x). |
| vrecps | VRECPS<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | Newton-Raphson step for reciprocal refinement: (2 - Vn * Vm). |
| vrev16 | VREV16<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Reverses bytes within 16-bit halfwords. |
| vrev32 | VREV32<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Reverses elements within 32-bit words. |
| vrev64 | VREV64<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Reverses elements within 64-bit doublewords. |
| vrinta | VRINTA<c>.F32 <Qd>, <Qm> | NEON 2-Reg | Rounds float to integral float (Nearest). |
| vrintn | VRINTN<c>.F32 <Qd>, <Qm> | NEON 2-Reg | Rounds float to integral float (Nearest Even). |
| vrintz | VRINTZ<c>.F32 <Qd>, <Qm> | NEON 2-Reg | Rounds float to integral float (Towards Zero). |
| vrshl | VRSHL<c>.<dt> <Qd>, <Qm>, <Qn> | NEON 3-Reg | Shifts left with rounding based on a register value. |
| vrshr | VRSHR<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts right with rounding based on immediate. |
| vrshrn | VRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | Shifts right, rounds, and narrows (2N -> N bits). |
| vrsqrte | VRSQRTE<c>.<dt> <Qd>, <Qm> | NEON 2-Reg | Estimates reciprocal square root (1/sqrt(x)). |
| vrsqrts | VRSQRTS<c>.F32 <Qd>, <Qn>, <Qm> | NEON 3-Reg | Newton-Raphson step for reciprocal sqrt refinement: (3 - Vn * Vm) / 2. |
| vrsra | VRSRA<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts right with rounding and adds to accumulator. |
| vrsubhn | VRSUBHN<c>.<dt> <Dd>, <Qn>, <Qm> | NEON 3-Reg | Subtracts wide elements, rounds, and returns high narrow half. |
| vshl | VSHL<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts elements left. |
| vshr | VSHR<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts elements right. |
| vshrn | VSHRN<c>.<dt> <Dd>, <Qm>, #<imm> | NEON Shift | Shifts right and narrows result. |
| vsli | VSLI<c>.<size> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts bits left and inserts into destination (merging). |
| vsra | VSRA<c>.<dt> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts elements right and adds to the destination accumulator. |
| vsri | VSRI<c>.<size> <Qd>, <Qm>, #<imm> | NEON Shift | Shifts bits right and inserts into destination. |
| vst1 | VST1<c>.<size> <list>, [<Rn>]{!} | NEON Store | Stores vector data to memory. |
| vst3 | VST3<c>.<size> <list>, [<Rn>]{!} | NEON Store | Interleaves and stores three registers into memory (e.g., RGB). |
| vst4 | VST4<c>.<size> <list>, [<Rn>]{!} | NEON Store | Interleaves and stores four registers into memory (e.g., RGBA). |
| vsub | VSUB<c>.<dt> <Qd>, <Qn>, <Qm> | NEON 3-Reg | Subtracts integer elements. |