vrsqrte

Vector Reciprocal Square Root Estimate

VRSQRTE<c>.<dt> <Qd>, <Qm>

Estimates reciprocal square root (1/sqrt(x)).

Details

Computes a vector reciprocal square root estimate (1/√x) for each element in the source register and stores the result in the destination register. This is a Newton-Raphson reciprocal square root estimate; the result serves as a starting point for iterative refinement. Condition flags (N, Z, C, V) are not affected. Executes in A32/T32 with NEON extension; requires FPEXC.EN = 1 for floating-point operation.

Pseudocode Operation

for i = 0 to 127 by element_size:
  element ← Qm[i+element_size-1:i]
  Qd[i+element_size-1:i] ← RecipSqrtEstimate(element)

Example

VRSQRTE.dt q0, q2

Encoding

Binary Layout
111100111
D
11
size
11
Vd
0
10
F
1
1
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xF3B304C0
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B30480 VRSQRTE{<c>}{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 11 | Vd | 0 | 10 | F | 1 | 0 | M | 0 | Vm
0xF3B304C0 VRSQRTE{<c>}{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 11 | Vd | 0 | 10 | F | 1 | 1 | M | 0 | Vm
0xFFB30480 VRSQRTE{<c>}{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 11 | Vd | 0 | 10 | F | 1 | 0 | M | 0 | Vm
0xFFB304C0 VRSQRTE{<c>}{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 11 | Vd | 0 | 10 | F | 1 | 1 | M | 0 | Vm

Description

Vector Reciprocal Square Root Estimate finds an approximate reciprocal square root of each element in a vector, and places the results in a second vector. The operand and result elements are the same type, and can be floating-point numbers or unsigned integers. For details of the operation performed by this instruction see Floating-point reciprocal estimate and step. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            if floating_point then
                Elem[D[d+r],e,esize] = FPRSqrtEstimate(Elem[D[m+r],e,esize], StandardFPSCRValue());
            else
                Elem[D[d+r],e,esize] = UnsignedRSqrtEstimate(Elem[D[m+r],e,esize]);