ssubl
Signed Subtract Long
Subtracts signed narrow vectors, producing wider result.
Pseudocode Operation
for i = 0 to (128 >> (size+1)) - 1 do
op1 ← SignExtend(Vn[i], element_width)
op2 ← SignExtend(Vm[i], element_width)
Vd[i] ← op1 - op2
end for
Example
Encoding
Operands
-
Vd
Dest (Wide) -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register
Related
More in NEON (SIMD)
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E202000 | SSUBL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> | A64 | 0 | Q | 0 | 01110 | size | 1 | Rm | 00 | 1 | 000 | Rn | Rd |
Description
Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements. The SSUBL instruction extracts each source vector from the lower half of each source register. The SSUBL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part, datasize];
bits(datasize) operand2 = Vpart[m, part, datasize];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;
for e = 0 to elements-1
element1 = Int(Elem[operand1, e, esize], unsigned);
element2 = Int(Elem[operand2, e, esize], unsigned);
if sub_op then
sum = element1 - element2;
else
sum = element1 + element2;
Elem[result, e, 2*esize] = sum<2*esize-1:0>;
V[d, 2*datasize] = result;