fcvtzu

Floating-Point Convert to Unsigned Integer (Zero)

FCVTZU <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>}

Converts float to unsigned integer, rounding towards zero (Truncate).

Details

Converts a floating-point value to an unsigned integer, rounding towards zero (truncation). The source is read from a half-precision (H), single-precision (S), or double-precision (D) FP register, and the result is written to a 32-bit (W) or 64-bit (X) general-purpose register. An optional fixed-point shift parameter (fbits) can scale the result by 2^fbits. NZCV flags are not affected by this instruction. This is an AArch64-only instruction that executes at any privilege level.

Pseudocode Operation

if source_is_nan then
  result ← 0
else
  if fbits_present then
    result ← round_towards_zero(FP_to_unsigned_integer(Vn) × 2^fbits)
  else
    result ← round_towards_zero(FP_to_unsigned_integer(Vn))
Rd ← result

Example

FCVTZU Wd, Dn

Encoding

Binary Layout
0
0
0
11110
00
1
11
001
000000
Rn
Rd
 
Format FP Conversion
Opcode 0x1E390000
Extension Floating Point

Operands

  • Rd
    Int Dest
  • Vn
    Float Src
  • fbits
    Fixed Point

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7F00FC00 FCVTZU <V><d>, <V><n>, #<fbits> A64 01 | 1 | 111110 | immh | immb | 11111 | 1 | Rn | Rd
0x2F00FC00 FCVTZU <Vd>.<T>, <Vn>.<T>, #<fbits> A64 0 | Q | 1 | 011110 | immh | immb | 11111 | 1 | Rn | Rd
0x7EF9B800 FCVTZU <Hd>, <Hn> A64 01 | 1 | 11110 | 1 | 1111001101 | 1 | 10 | Rn | Rd
0x7EA1B800 FCVTZU <V><d>, <V><n> A64 01 | 1 | 11110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd
0x2EF9B800 FCVTZU <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 1 | 1111001101 | 1 | 10 | Rn | Rd
0x2EA1B800 FCVTZU <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd
0x1ED90000 FCVTZU <Wd>, <Hn>, #<fbits> A64 0 | 0 | 0 | 11110 | 11 | 0 | 11 | 001 | scale | Rn | Rd
0x9ED90000 FCVTZU <Xd>, <Hn>, #<fbits> A64 1 | 0 | 0 | 11110 | 11 | 0 | 11 | 001 | scale | Rn | Rd
0x1E190000 FCVTZU <Wd>, <Sn>, #<fbits> A64 0 | 0 | 0 | 11110 | 00 | 0 | 11 | 001 | scale | Rn | Rd
0x9E190000 FCVTZU <Xd>, <Sn>, #<fbits> A64 1 | 0 | 0 | 11110 | 00 | 0 | 11 | 001 | scale | Rn | Rd
0x1E590000 FCVTZU <Wd>, <Dn>, #<fbits> A64 0 | 0 | 0 | 11110 | 01 | 0 | 11 | 001 | scale | Rn | Rd
0x9E590000 FCVTZU <Xd>, <Dn>, #<fbits> A64 1 | 0 | 0 | 11110 | 01 | 0 | 11 | 001 | scale | Rn | Rd
0x1EF90000 FCVTZU <Wd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 11 | 001 | 000000 | Rn | Rd
0x9EF90000 FCVTZU <Xd>, <Hn> A64 1 | 0 | 0 | 11110 | 11 | 1 | 11 | 001 | 000000 | Rn | Rd

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(decode_fltsize) fltval;
bits(intsize) intval;

fltval = V[n, decode_fltsize];
intval = FPToFixed(fltval, 0, TRUE, FPCR, rounding, intsize);
X[d, intsize] = intval;