udiv

Unsigned Divide (A32)

UDIV<c> <Rd>, <Rn>, <Rm>

Unsigned integer division.

Details

Unsigned Divide performs unsigned integer division of Rn (dividend) by Rm (divisor), storing the quotient in Rd. Division by zero does not raise an exception; the result is architecturally unpredictable. No condition flags are modified. UDIV is available only in A32 with the Divide extension (ARMv7-R, ARMv7-A with hardware divide).

Pseudocode Operation

if Rm == 0 then
  Rd ← UNPREDICTABLE;
else
  Rd ← UnsignedDivide(Rn, Rm);
endif;

Example

UDIV r0, r1, r2

Encoding

Binary Layout
cond
01110
011
Rd
1111
Rm
000
1
Rn
 
Format Data Proc
Opcode 0x0730F010
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    Dividend
  • Rm
    Divisor

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0730F010 UDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01110 | 011 | Rd | 1111 | Rm | 000 | 1 | Rn
0xFBB0F0F0 UDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110111 | 011 | Rn | 1111 | Rd | 1111 | Rm

Description

Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See Divide instructions for more information about this instruction.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    integer result;
    if UInt(R[m]) == 0 then
        result = 0;
    else
        result = RoundTowardsZero(Real(UInt(R[n])) / Real(UInt(R[m])));
    R[d] = result<31:0>;