vswp

Vector Swap

VSWP<c> <Qd>, <Qm>

Swaps the contents of two vectors.

Details

Vector Swap exchanges the entire contents of two SIMD registers. The register sizes (64-bit or 128-bit) are determined by the Q bit in the encoding. This is a data movement operation with no arithmetic or comparison; no condition flags are affected.

Pseudocode Operation

temp ← Qd
Qd ← Qm
Qm ← temp

Example

VSWP q0, q2

Encoding

Binary Layout
111100111
D
11
00
10
Vd
0
0000
0
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xF3B20000
Extension NEON (SIMD)

Operands

  • Qd
    Reg 1
  • Qm
    Reg 2

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B20000 VSWP{<c>}{<q>}{.<dt>} <Dd>, <Dm> A32 111100111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 0 | M | 0 | Vm
0xF3B20040 VSWP{<c>}{<q>}{.<dt>} <Qd>, <Qm> A32 111100111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 1 | M | 0 | Vm
0xFFB20000 VSWP{<c>}{<q>}{.<dt>} <Dd>, <Dm> T32 111111111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 0 | M | 0 | Vm
0xFFB20040 VSWP{<c>}{<q>}{.<dt>} <Qd>, <Qm> T32 111111111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 1 | M | 0 | Vm

Description

Vector Swap exchanges the contents of two vectors. The vectors can be either doubleword or quadword. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        if d == m then
            D[d+r] = bits(64) UNKNOWN;
        else
            D[d+r] = Din[m+r];
            D[m+r] = Din[d+r];