vswp

Vector Swap

VSWP<c> <Qd>, <Qm>

Swaps the contents of two vectors.

Pseudocode Operation

temp ← Qd
Qd ← Qm
Qm ← temp

Example

VSWP q0, q2

Encoding

Binary Layout

111100111

31:23

D

22

11

21:20

00

19:18

10

17:16

Vd

15:12

0

11

0000

10:7

0

6

M

5

0

4

Vm

3:0

 

Format NEON 2-Reg

Opcode 0xF3B20000

Extension NEON (SIMD)

Operands

• Qd
  Reg 1
• Qm
  Reg 2

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3B20000	VSWP{<c>}{<q>}{.<dt>} <Dd>, <Dm>		A32		111100111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 0 | M | 0 | Vm
0xF3B20040	VSWP{<c>}{<q>}{.<dt>} <Qd>, <Qm>		A32		111100111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 1 | M | 0 | Vm
0xFFB20000	VSWP{<c>}{<q>}{.<dt>} <Dd>, <Dm>		T32		111111111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 0 | M | 0 | Vm
0xFFB20040	VSWP{<c>}{<q>}{.<dt>} <Qd>, <Qm>		T32		111111111 | D | 11 | 00 | 10 | Vd | 0 | 0000 | 1 | M | 0 | Vm

Description

Vector Swap exchanges the contents of two vectors. The vectors can be either doubleword or quadword. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        if d == m then
            D[d+r] = bits(64) UNKNOWN;
        else
            D[d+r] = Din[m+r];
            D[m+r] = Din[d+r];