vrintz

Vector Round Floating-Point (Zero)

VRINTZ<c>.F32 <Qd>, <Qm>

Rounds float to integral float (Towards Zero).

Details

Rounds each 32-bit floating-point element in the source vector towards zero to an integer value, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.

Pseudocode Operation

for i = 0 to 3
  Qd[i] ← RoundTowardsZero(Qm[i])
end for

Example

VRINTZ.F32 q0, q2

Encoding

Binary Layout
cond
11101
D
11
0
110
Vd
10
10
1
1
M
0
Vm
 
Format NEON 2-Reg
Opcode 0x0EB60AC0
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B20580 VRINTZ{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 1011 | 0 | M | 0 | Vm
0xF3B205C0 VRINTZ{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 1011 | 1 | M | 0 | Vm
0xFFB20580 VRINTZ{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 1011 | 0 | M | 0 | Vm
0xFFB205C0 VRINTZ{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 1011 | 1 | M | 0 | Vm
0x0EB609C0 VRINTZ{<c>}{<q>}.F16 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0x0EB60AC0 VRINTZ{<c>}{<q>}.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm
0x0EB60BC0 VRINTZ{<c>}{<q>}.F64 <Dd>, <Dm> A32 cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm
0xEEB609C0 VRINTZ{<c>}{<q>}.F16 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 110 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0xEEB60AC0 VRINTZ{<c>}{<q>}.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 110 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm
0xEEB60BC0 VRINTZ{<c>}{<q>}.F64 <Dd>, <Dm> T32 111011101 | D | 11 | 0 | 110 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm

Description

Round floating-point to integer towards Zero rounds a floating-point value to an integral floating-point value of the same size, using the Round towards Zero rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

Operation

if ConditionPassed() then
    EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
    case esize of
        when 16
            S[d] = Zeros(16) : FPRoundInt(S[m]<15:0>, FPSCR[], rounding, exact);
        when 32
            S[d] = FPRoundInt(S[m], FPSCR[], rounding, exact);
        when 64
            D[d] = FPRoundInt(D[m], FPSCR[], rounding, exact);