ldrh

Load Register Halfword (Register)

LDRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Loads a halfword from memory (zero-extended) using register offset.

Details

Loads an unsigned halfword from memory using register offset with optional extension and zero-extends it to 32 bits. No condition flags are affected. This is an AArch64 Base instruction that executes in all privilege levels.

Pseudocode Operation

offset ← ExtendReg(Rm, extend_type, shift_amount);
address ← Xn + offset;
Wt ← ZeroExtend(Mem[address, 2], 32);

Example

LDRH w3, [x1, Rm ]

Encoding

Binary Layout
01
111
0
00
01
1
Rm
option
S
10
Rn
Rt
 
Format Load/Store
Opcode 0x78600800
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • Rm
    Offset Reg

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x78400400 LDRH <Wt>, [<Xn|SP>], #<simm> A64 01 | 111 | 0 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x78400C00 LDRH <Wt>, [<Xn|SP>, #<simm>]! A64 01 | 111 | 0 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x79400000 LDRH <Wt>, [<Xn|SP>{, #<pimm>}] A64 01 | 111 | 0 | 01 | 01 | imm12 | Rn | Rt
0x78600800 LDRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] A64 01 | 111 | 0 | 00 | 01 | 1 | Rm | option | S | 10 | Rn | Rt

Description

Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) offset = ExtendReg(m, extend_type, shift, 64);
bits(64) address;
bits(16) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, TRUE);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = Mem[address, 2, accdesc];
X[t, 32] = ZeroExtend(data, 32);