vqshl

Vector Saturating Shift Left (Immediate)

VQSHL<c>.<dt> <Qd>, <Qm>, #<imm>

Shifts left with saturation based on immediate.

Details

Vector Saturating Shift Left (Immediate) shifts each element in Qm left by an immediate value, saturating the result to the range of the operand data type. The immediate is a signed value encoded in imm6; positive values shift left, negative values (when sign-extended) would shift right. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.

Pseudocode Operation

shift_amount ← SignExtend(imm6, 6)
for i = 0 to elements-1 do
  result ← SatQ(Qm[i] << shift_amount, esize)
  Qd[i] ← result

Example

VQSHL.dt q0, q2, #16

Encoding

Binary Layout
1111001
U
1
D
imm6
Vd
011
1
L
0
M
1
Vm
 
Format NEON Shift
Opcode 0xF2800710
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800710 VQSHL{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm> A32 1111001 | U | 1 | D | imm6 | Vd | 011 | 1 | L | 0 | M | 1 | Vm
0xF2800750 VQSHL{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm> A32 1111001 | U | 1 | D | imm6 | Vd | 011 | 1 | L | 1 | M | 1 | Vm
0xEF800710 VQSHL{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm> T32 111 | U | 11111 | D | imm6 | Vd | 011 | 1 | L | 0 | M | 1 | Vm
0xEF800750 VQSHL{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm> T32 111 | U | 11111 | D | imm6 | Vd | 011 | 1 | L | 1 | M | 1 | Vm
0xF2000410 VQSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn> A32 1111001 | U | 0 | D | size | Vn | Vd | 0100 | N | 0 | M | 1 | Vm
0xF2000450 VQSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn> A32 1111001 | U | 0 | D | size | Vn | Vd | 0100 | N | 1 | M | 1 | Vm
0xEF000410 VQSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn> T32 111 | U | 11110 | D | size | Vn | Vd | 0100 | N | 0 | M | 1 | Vm
0xEF000450 VQSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn> T32 111 | U | 11110 | D | size | Vn | Vd | 0100 | N | 1 | M | 1 | Vm

Description

Vector Saturating Shift Left (immediate) takes each element in a vector of integers, left shifts them by an immediate value, and places the results in a second vector. The operand elements must all be the same size, and can be any one of: The result elements are the same size as the operand elements. If the operand elements are signed, the results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            operand = Int(Elem[D[m+r],e,esize], src_unsigned);
            (result, sat) = SatQ(operand << shift_amount, esize, dest_unsigned);
            Elem[D[d+r],e,esize] = result;
            if sat then FPSCR.QC = '1';