adds
Add and Set Flags (Immediate)
ADDS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>}
Adds immediate and updates flags.
Pseudocode Operation
imm_val ← imm12 << (sh * 12)
result ← Wn + imm_val
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Wn, imm_val)
V ← OverflowFrom(Wn, imm_val)
Example
ADDS w0, Wn, #16
Encoding
Binary Layout
0
31
0
30
1
29
100010
28:23
sh
22
imm12
21:10
Rn
9:5
Rd
4:0
Operands
-
Wd
Destination 32-bit integer register -
Wn
First source / base 32-bit integer register -
imm
Imm
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x2B200000 | ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} | A64 | 0 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd | ||
| 0xAB200000 | ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}} | A64 | 1 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd | ||
| 0x31000000 | ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>} | A64 | 0 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd | ||
| 0xB1000000 | ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>} | A64 | 1 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd | ||
| 0x2B000000 | ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} | A64 | 0 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd | ||
| 0xAB000000 | ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} | A64 | 1 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd |
Description
Add (immediate), setting flags, adds a register value and an optionally-shifted immediate value, and writes the result to the destination register. It updates the condition flags based on the result.
Operation
bits(datasize) result; bits(datasize) operand1 = if n == 31 then SP[]<datasize-1:0> else X[n, datasize]; bits(4) nzcv; (result, nzcv) = AddWithCarry(operand1, imm, '0'); PSTATE.<N,Z,C,V> = nzcv; X[d, datasize] = result;