cinv

Conditional Invert

CINV <Wd>, <Wn>, <cond>

Invert register bits if condition is true, else copy. (Alias for CSINV)

Pseudocode Operation

if ConditionHolds(cond) then
  Wd ← ~Wn
else
  Wd ← Wn

Example

CINV w0, w1, cond

Encoding

Binary Layout

0

31

1

30

0

29

11010100

28:21

Rm

20:16

cond

15:12

0

11

0

10

Rn

9:5

Rd

4:0

 

Format Cond Select

Opcode 0x5A800000

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• cond
  Condition

Related

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x5A800000	CINV <Wd>, <Wn>, <invcond>		A64		0 | 1 | 0 | 11010100 | Rm | cond | 0 | 0 | Rn | Rd
0xDA800000	CINV <Xd>, <Xn>, <invcond>		A64		1 | 1 | 0 | 11010100 | Rm | cond | 0 | 0 | Rn | Rd

Description

Conditional Invert returns, in the destination register, the bitwise inversion of the value of the source register if the condition is TRUE, and otherwise returns the value of the source register.