stm

Store Multiple (Thumb)

STM <Rn>!, <registers>

Store multiple registers (Thumb 16-bit).

Pseudocode Operation

address ← Rn
for each register in register_list (in ascending order):
  [address] ← register
  address ← address + 4
Rn ← address

Example

STM r1!, registers

Encoding

Binary Layout

1100

15:12

10:8

register_list

7:0

Format Thumb Store Multiple

Opcode 0xC000

Extension T32 (Base)

Operands

Rn
First source / base general-purpose register
registers
List

Other forms of stm

stm Store Multiple (A32)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x08800000	STM{IA}{<c>}{<q>} <Rn>{!}, <registers>	A32	cond \| 100 \| 0 \| 1 \| 0 \| W \| 0 \| Rn \| register_list
0xC000	STM{IA}{<c>}{<q>} <Rn>!, <registers>	T32	1100 \| 0 \| Rn \| register_list
0xE8800000	STM{IA}{<c>}.W <Rn>{!}, <registers>	T32	1110100 \| 01 \| 0 \| W \| 0 \| Rn \| 0 \| M \| register_list
0x08400000	STM{<amode>}{<c>}{<q>} <Rn>, <registers>^	A32	cond \| 100 \| P \| U \| 1 \| 0 \| 0 \| Rn \| register_list
0x08000000	STMDA{<c>}{<q>} <Rn>{!}, <registers>	A32	cond \| 100 \| 0 \| 0 \| 0 \| W \| 0 \| Rn \| register_list
0x09000000	STMDB{<c>}{<q>} <Rn>{!}, <registers>	A32	cond \| 100 \| 1 \| 0 \| 0 \| W \| 0 \| Rn \| register_list
0xE9000000	STMDB{<c>}{<q>} <Rn>{!}, <registers>	T32	1110100 \| 10 \| 0 \| W \| 0 \| Rn \| 0 \| M \| register_list
0x09800000	STMIB{<c>}{<q>} <Rn>{!}, <registers>	A32	cond \| 100 \| 1 \| 1 \| 0 \| W \| 0 \| Rn \| register_list

Description

Store Multiple (Increment After, Empty Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the last of those locations can optionally be written back to the base register. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also Encoding of lists of general-purpose registers and the PC. Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see FEAT_LSMAOC. For details of related system instructions see STM (User registers).

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    for i = 0 to 14
        if registers<i> == '1' then
            if i == n && wback && i != LowestSetBit(registers) then
                MemS[address,4] = bits(32) UNKNOWN;  // Only possible for encodings T1 and A1
            else
                MemS[address,4] = R[i];
            address = address + 4;
    if registers<15> == '1' then  // Only possible for encoding A1
        MemS[address,4] = PCStoreValue();
    if wback then R[n] = R[n] + 4*BitCount(registers);

stm