bfsub

BFloat16 Subtract

BFSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Subtracts BFloat16 elements.

Details

Subtracts BFloat16 (16-bit) elements of one SVE register from another under predicate control and stores the result in the destination register. Floating-point exceptions may be generated; condition flags are unaffected. Requires FEAT_SVE_B16B16; AArch64 only.

Pseudocode Operation

for i = 0 to VL/16 - 1
  if Pg[i]
    Zdn[i] ← FP_Sub(Zdn[i], Zm[i], RMode_TONEAREST)
  else
    Zdn[i] ← Zdn[i]

Example

BFSUB z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout

01100101

000

100

Zdn

Format SVE BFloat16

Opcode 0x65018000

Extension FEAT_SVE_B16B16

Operands

Zdn
Dest/Src
Pg
Mask
Zm
Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x65018000	BFSUB <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H	A64	01100101 \| 0 \| 0 \| 00 \| 000 \| 1 \| 100 \| Pg \| Zm \| Zdn
0x65000400	BFSUB <Zd>.H, <Zn>.H, <Zm>.H	A64	01100101 \| 0 \| 0 \| 0 \| Zm \| 000 \| 00 \| 1 \| Zn \| Zd
0xC1E41C08	BFSUB ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H }	A64	110000011 \| 1 \| 1001000 \| Rv \| 111 \| Zm \| 00 \| 1 \| off3
0xC1E51C08	BFSUB ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H }	A64	110000011 \| 1 \| 1001010 \| Rv \| 111 \| Zm \| 000 \| 1 \| off3

Description

Subtract active BFloat16 elements of the second source vector from corresponding BFloat16 elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified. This instruction follows SVE2.1 non-widening BFloat16 numerical behaviors. ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV 16;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, 16) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    bits(16) element1 = Elem[operand1, e, 16];
    if ActivePredicateElement(mask, e, 16) then
        bits(16) element2 = Elem[operand2, e, 16];
        Elem[result, e, 16] = BFSub(element1, element2, FPCR);
    else
        Elem[result, e, 16] = element1;

Z[dn, VL] = result;