vpadd

Vector Pairwise Add

VPADD<c>.<dt> <Dd>, <Dn>, <Dm>

Adds adjacent pairs of elements.

Pseudocode Operation

case dt of
  when I8:  for i = 0 to 3: Dd[i] ← Dn[2*i] + Dn[2*i+1] + Dm[2*i] + Dm[2*i+1]
  when I16: for i = 0 to 1: Dd[i] ← Dn[2*i] + Dn[2*i+1] + Dm[2*i] + Dm[2*i+1]
  when I32: Dd[0] ← Dn[0] + Dn[1]; Dd[1] ← Dm[0] + Dm[1]
  when F32: Dd[0] ← Dn[0] + Dn[1]; Dd[1] ← Dm[0] + Dm[1]

Example

VPADD.dt d0, d1, d2

Encoding

Binary Layout

1111001

31:25

size

21:20

19:16

15:12

1011

11:8

3:0

Format NEON 3-Reg

Opcode 0xF2000B10

Extension NEON (SIMD)

Operands

Dd
Destination 64-bit SIMD/FP register
Dn
First source 64-bit SIMD/FP register
Dm
Second source 64-bit SIMD/FP register

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0xF3000D00	VPADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>	A32	1111001 \| 1 \| 0 \| D \| 0 \| sz \| Vn \| Vd \| 1101 \| N \| Q \| M \| 0 \| Vm
0xFF000D00	VPADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>	T32	111 \| 1 \| 11110 \| D \| 0 \| sz \| Vn \| Vd \| 1101 \| N \| Q \| M \| 0 \| Vm
0xF2000B10	VPADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>	A32	1111001 \| 0 \| 0 \| D \| size \| Vn \| Vd \| 1011 \| N \| Q \| M \| 1 \| Vm
0xEF000B10	VPADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>	T32	111 \| 0 \| 11110 \| D \| size \| Vn \| Vd \| 1011 \| N \| Q \| M \| 1 \| Vm

Description

Vector Pairwise Add (integer) adds adjacent pairs of elements of two vectors, and places the results in the destination vector. The operands and result are doubleword vectors. The operand and result elements must all be the same type, and can be 8-bit, 16-bit, or 32-bit integers. There is no distinction between signed and unsigned integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    bits(64) dest;
    h = elements DIV 2;

    for e = 0 to h-1
        Elem[dest,e,esize]   = Elem[D[n],2*e,esize] + Elem[D[n],2*e+1,esize];
        Elem[dest,e+h,esize] = Elem[D[m],2*e,esize] + Elem[D[m],2*e+1,esize];

    D[d] = dest;