vqshrn

Vector Saturating Shift Right Narrow

VQSHRN<c>.<dt> <Dd>, <Qm>, #<imm>

Shifts right, saturates, and narrows.

Details

Vector Saturating Shift Right Narrow shifts each element in Qm right by an immediate value, saturates to the range of the narrower result type, then packs the narrowed results into the destination Dd. This operation reduces element size by half and narrows the register from 128-bit to 64-bit. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.

Pseudocode Operation

shift_amount ← imm6
for i = 0 to narrow_elements-1 do
  wide_value ← Qm[i]
  shifted ← wide_value >> shift_amount
  result ← SatQ(shifted, narrow_esize)
  Dd[i] ← result

Example

VQSHRN.dt d0, q2, #16

Encoding

Binary Layout
1111001
U
1
D
imm6
Vd
100
1
0
0
M
1
Vm
 
Format NEON Shift
Opcode 0xF2800910
Extension NEON (SIMD)

Operands

  • Dd
    Dest Narrow
  • Qm
    Src Wide
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800910 VQSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm> A32 1111001 | U | 1 | D | imm6 | Vd | 100 | 1 | 0 | 0 | M | 1 | Vm
0xEF800910 VQSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm> T32 111 | U | 11111 | D | imm6 | Vd | 100 | 1 | 0 | 0 | M | 1 | Vm
0xF3B20280 VQSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 A32 111100111 | D | 11 | size | 10 | Vd | 0 | 010 | op | M | 0 | Vm
0xFFB20280 VQSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 T32 111111111 | D | 11 | size | 10 | Vd | 0 | 010 | op | M | 0 | Vm

Description

Vector Saturating Shift Right, Narrow takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the truncated results in a doubleword vector. For rounded results, see VQRSHRN and VQRSHRUN. The operand elements must all be the same size, and can be any one of: The result elements are half the width of the operand elements. If the operand elements are signed, the results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        operand = Int(Elem[Qin[m>>1],e,2*esize], src_unsigned);
        (result, sat) = SatQ(operand >> shift_amount, esize, dest_unsigned);
        Elem[D[d],e,esize] = result;
        if sat then FPSCR.QC = '1';