vmmla

Matrix Multiply Accumulate (A32)

VMMLA<c>.<dt> <Qd>, <Qn>, <Qm>

Matrix multiply-accumulate (BFloat16/Int8).

Details

Vector Matrix Multiply-Accumulate performs a 4×4 matrix multiply-accumulate operation on either 8-bit integers or BFloat16 values, with results accumulated into Qd. When sz=0, operates on signed/unsigned 8-bit elements; when sz=1, operates on BFloat16 elements. No condition flags are modified. This instruction requires the NEON Matrix Multiply extension and executes in A32 (ARM) state.

Pseudocode Operation

if sz == 0:
  Qd ← Qd + MatMul_Int8(Qn, Qm)  (4x4 matrix multiply of int8 elements)
else:
  Qd ← Qd + MatMul_BF16(Qn, Qm) (4x4 matrix multiply of bfloat16 elements)

Example

VMMLA.dt q0, q1, q2

Encoding

Binary Layout
1111110
00
D
0
0
Vn
Vd
1
1
0
0
N
1
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xFC000C40
Extension NEON (MatMul)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xFC000C40 VMMLA{<q>}.BF16 <Qd>, <Qn>, <Qm> A32 1111110 | 00 | D | 0 | 0 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 0 | Vm

Description

BFloat16 floating-point matrix multiply-accumulate. This instruction multiplies the 2x4 matrix of BF16 values in the first 128-bit source vector by the 4x2 BF16 matrix in the second 128-bit source vector. The resulting 2x2 single-precision matrix product is then added destructively to the 2x2 single-precision matrix in the 128-bit destination vector. This is equivalent to performing a 4-way dot product per destination element. The instruction does not update the FPSCR exception status.

Operation

CheckAdvSIMDEnabled();

bits(128) op1 = Q[n>>1];
bits(128) op2 = Q[m>>1];
bits(128) acc = Q[d>>1];

Q[d>>1] = BFMatMulAdd(acc, op1, op2);