veor

Vector Exclusive OR

VEOR<c> <Qd>, <Qn>, <Qm>

Bitwise XOR of two vectors.

Pseudocode Operation

for i = 0 to 127
  Qd[i] ← Qn[i] XOR Qm[i]

Example

VEOR q0, q1, q2

Encoding

Binary Layout

1111001

31:25

1

24

0

23

D

22

00

21:20

Vn

19:16

Vd

15:12

0001

11:8

N

7

0

6

M

5

1

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF3000110

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qn
  First source 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3000110	VEOR{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>		A32		1111001 | 1 | 0 | D | 00 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF3000150	VEOR{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>		A32		1111001 | 1 | 0 | D | 00 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xFF000110	VEOR{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>		T32		111 | 1 | 11110 | D | 00 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xFF000150	VEOR{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>		T32		111 | 1 | 11110 | D | 00 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm

Description

Vector Bitwise Exclusive-OR performs a bitwise exclusive-OR operation between two registers, and places the result in the destination register. The operand and result registers can be quadword or doubleword. They must all be the same size. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        D[d+r] = D[n+r] EOR D[m+r];