sdot

Signed Dot Product (A32)

SDOT<c>.S8 <Qd>, <Qn>, <Qm>

Signed Dot Product (vector by vector).

Details

Signed Dot Product computes the dot product of four signed 8-bit integer elements from Qn and Qm, accumulating the result into the corresponding 32-bit element of Qd. Four separate dot products are computed in parallel across the 128-bit vectors. No condition flags are modified. This instruction requires the NEON Dot Product extension and executes in A32 (ARM) state.

Pseudocode Operation

for i in [0, 1, 2, 3]:
  Qd[i*32+31:i*32] ← Qd[i*32+31:i*32] + SignedDotProduct(Qn[i*32+31:i*32], Qm[i*32+31:i*32])

Example

SDOT.S8 q0, q1, q2

Encoding

Binary Layout
01000100000
Zm
11001
0
Zn
Zda
 
Format NEON 3-Reg
Opcode 0x4400C800
Extension NEON (DotProd)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F00E000 SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] A64 0 | Q | 0 | 01111 | size | L | M | Rm | 1110 | H | 0 | Rn | Rd
0x0E009400 SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 0 | 01110 | size | 0 | Rm | 1 | 0010 | 1 | Rn | Rd
0x4400C800 SDOT <Zda>.S, <Zn>.H, <Zm>.H A64 01000100000 | Zm | 11001 | 0 | Zn | Zda
0x4480C800 SDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] A64 01000100100 | i2 | Zm | 11001 | 0 | Zn | Zda
0x44000000 SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> A64 01000100 | size | 0 | Zm | 00000 | 0 | Zn | Zda
0x44A00000 SDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] A64 01000100 | 1 | 0 | 1 | i2 | Zm | 00000 | 0 | Zn | Zda
0x44E00000 SDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>] A64 01000100 | 1 | 1 | 1 | i1 | Zm | 00000 | 0 | Zn | Zda
0xC1501000 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 0 | 0 | 0 | off3
0xC1509000 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 0 | 0 | 0 | off3
0xC1601408 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H A64 11 | 0000010110 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3
0xC1701408 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H A64 11 | 0000010111 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3
0xC1E01408 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } A64 11 | 000001111 | Zm | 00 | Rv | 101 | Zn | 0 | 0 | 1 | off3
0xC1E11408 SDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } A64 11 | 000001111 | Zm | 010 | Rv | 101 | Zn | 00 | 0 | 1 | off3
0xC1501020 SDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 1 | 0 | 0 | off3

Description

The signed integer dot product instruction computes the dot product of a group of two signed 16-bit integer values held in each 32-bit element of the first source vector multiplied by a group of two signed 16-bit integer values in the corresponding 32-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit element of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[da, VL];
bits(VL) result;

for e = 0 to elements-1
    bits(esize) res = Elem[operand3, e, esize];
    for i = 0 to 1
        integer element1 = SInt(Elem[operand1, 2 * e + i, esize DIV 2]);
        integer element2 = SInt(Elem[operand2, 2 * e + i, esize DIV 2]);
        res = res + element1 * element2;
    Elem[result, e, esize] = res;

Z[da, VL] = result;