add
Add (Immediate 64-bit)
ADD <Xd|SP>, <Xn|SP>, #<imm> {, lsl #<shift>}
Adds a 64-bit register value and an immediate value.
Details
Adds a 12-bit immediate value (optionally shifted left by 0 or 12 bits) to a 64-bit register and stores the result in the destination register. Condition flags (N, Z, C, V) are not affected by this instruction. SP may be used as source or destination.
Pseudocode Operation
Xd ← Xn + (imm << (sh * 12))Example
ADD x0, x1, #16
Encoding
Binary Layout
1
0
0
100010
sh
imm12
Rn
Rd
Operands
-
Xd
Destination 64-bit integer register -
Xn
First source / base 64-bit integer register -
imm
Signed immediate value
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0B200000 | ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} | A64 | 0 | 0 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd | ||
| 0x8B200000 | ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}} | A64 | 1 | 0 | 0 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd | ||
| 0x11000000 | ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>} | A64 | 0 | 0 | 0 | 100010 | sh | imm12 | Rn | Rd | ||
| 0x91000000 | ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>} | A64 | 1 | 0 | 0 | 100010 | sh | imm12 | Rn | Rd | ||
| 0x0B000000 | ADD <Wd>, <Wn>, <Wm>{, <shift> #<amount>} | A64 | 0 | 0 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd | ||
| 0x8B000000 | ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>} | A64 | 1 | 0 | 0 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd | ||
| 0x5EE08400 | ADD D<d>, D<n>, D<m> | A64 | 01 | 0 | 11110 | 11 | 1 | Rm | 10000 | 1 | Rn | Rd | ||
| 0x0E208400 | ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | size | 1 | Rm | 10000 | 1 | Rn | Rd | ||
| 0xC120A300 | ADD { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101000 | 11000 | Zdn | 0 | ||
| 0xC120AB00 | ADD { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101010 | 11000 | Zdn | 0 | 0 | ||
| 0x04000000 | ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 000 | 00 | 0 | 000 | Pg | Zm | Zdn | ||
| 0x2520C000 | ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} | A64 | 00100101 | size | 100 | 00 | 0 | 11 | sh | imm8 | Zdn | ||
| 0x04200000 | ADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 1 | Zm | 000 | 00 | 0 | Zn | Zd | ||
| 0xC1A01C10 | ADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } | A64 | 110000011 | sz | 1000000 | Rv | 111 | Zm | 01 | 0 | off3 |
Description
Add (immediate) adds a register value and an optionally-shifted immediate value, and writes the result to the destination register.
Operation
bits(datasize) result;
bits(datasize) operand1 = if n == 31 then SP[]<datasize-1:0> else X[n, datasize];
(result, -) = AddWithCarry(operand1, imm, '0');
if d == 31 then
SP[] = ZeroExtend(result, 64);
else
X[d, datasize] = result;