ldxr

Load Exclusive Register

LDXR <Wt>, [<Xn|SP>]

Loads a word and marks physical address as exclusive access.

Details

Loads a 32-bit word from memory at the address in Xn|SP and marks the physical address as exclusive for subsequent store-exclusive operations. No condition flags are affected. This is an AArch64-only instruction that requires Execute permission on the accessed memory and generates an alignment fault if the address is not word-aligned.

Pseudocode Operation

address ← [Xn|SP]
Wt ← [address]
ExclusiveMonitors.MarkExclusive(address, ProcessorID, 4)

Example

LDXR w3, [x1]

Encoding

Binary Layout
10
0010000
1
0
11111
0
11111
Rn
Rt
 
Format Load/Store Excl
Opcode 0x885F7C00
Extension Base (Atomic)

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x885F7C00 LDXR <Wt>, [<Xn|SP>{, #0}] A64 10 | 0010000 | 1 | 0 | 11111 | 0 | 11111 | Rn | Rt
0xC85F7C00 LDXR <Xt>, [<Xn|SP>{, #0}] A64 11 | 0010000 | 1 | 0 | 11111 | 0 | 11111 | Rn | Rt

Description

Load Exclusive Register derives an address from a base register value, loads a 32-bit word or a 64-bit doubleword from memory, and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(elsize) data;
constant integer dbytes = elsize DIV 8;

AccessDescriptor accdesc = CreateAccDescExLDST(MemOp_LOAD, FALSE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

// Tell the Exclusives monitors to record a sequence of one or more atomic
// memory reads from virtual address range [address, address+dbytes-1].
// The Exclusives monitor will only be set if all the reads are from the
// same dbytes-aligned physical address, to allow for the possibility of
// an atomicity break if the translation is changed between reads.
AArch64.SetExclusiveMonitors(address, dbytes);

data = Mem[address, dbytes, accdesc];
X[t, regsize] = ZeroExtend(data, regsize);