xtn

Vector Extract Narrow

XTN <Vd>.<Tb>, <Vn>.<Ta>

Reads elements, narrows them, and writes to lower half of destination.

Details

Extracts elements from Vn, narrows them by taking the least significant bits according to the narrower type, and writes them to the lower half of Vd. The upper half of Vd is zeroed. This is a type conversion with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+).

Pseudocode Operation

esize_src ← 8 << size;
esize_dst ← esize_src / 2;
for e = 0 to esize_dst-1
  element ← Vn[e * esize_src +: esize_src];
  result[e * esize_dst +: esize_dst] ← element[0 +: esize_dst];
Vd[0 +: 64] ← result[0 +: 64];
Vd[64 +: 64] ← 0;

Example

XTN v0.4s.Tb, v1.4s.Ta

Encoding

Binary Layout
0
Q
0
01110
size
10000
10010
10
Rn
Rd
 
Format SIMD Shift Imm
Opcode 0x0E212800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E212800 XTN{2} <Vd>.<Tb>, <Vn>.<Ta> A64 0 | Q | 0 | 01110 | size | 10000 | 10010 | 10 | Rn | Rd

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The XTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the XTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand = V[n, 2*datasize];
bits(datasize) result;
bits(2*esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, 2*esize];
    Elem[result, e, esize] = element<esize-1:0>;
Vpart[d, part, datasize] = result;