vmull

Vector Multiply Long

VMULL<c>.<dt> <Qd>, <Dn>, <Dm>

Multiplies N-bit elements producing 2N-bit results.

Details

Multiplies N-bit elements from two 64-bit source registers to produce 2N-bit results in a 128-bit destination register. The sz field specifies 8, 16, or 32-bit source element width. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to (64 / source_element_width) - 1:
  Qd[i] ← Dn[i] × Dm[i]

Example

VMULL.dt q0, d1, d2

Encoding

Binary Layout
1111001
U
1
D
size
Vn
Vd
11
op
0
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2800C00
Extension NEON (SIMD)

Operands

  • Qd
    Dest Wide
  • Dn
    First source 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800C00 VMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm> A32 1111001 | U | 1 | D | size | Vn | Vd | 11 | op | 0 | N | 0 | M | 0 | Vm
0xEF800C00 VMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm> T32 111 | U | 11111 | D | size | Vn | Vd | 11 | op | 0 | N | 0 | M | 0 | Vm
0xF2800A40 VMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>[<index>] A32 1111001 | U | 1 | D | size | Vn | Vd | 1010 | N | 1 | M | 0 | Vm
0xEF800A40 VMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>[<index>] T32 111 | U | 11111 | D | size | Vn | Vd | 1010 | N | 1 | M | 0 | Vm

Description

Vector Multiply Long multiplies corresponding elements in two vectors. The destination vector elements are twice as long as the elements that are multiplied. For information about multiplying polynomials see Polynomial arithmetic over {0, 1}. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Elem[Din[n+r],e,esize];  op1val = Int(op1, unsigned);
            op2 = Elem[Din[m+r],e,esize];  op2val = Int(op2, unsigned);
            bits(2 * esize) product;
            if polynomial then
                product = PolynomialMult(op1,op2);
            else
                product = (op1val*op2val)<2*esize-1:0>;
            if long_destination then
                Elem[Q[d>>1],e,2*esize] = product;
            else
                Elem[D[d+r],e,esize] = product<esize-1:0>;