vjcvt

Vector Javascript Convert (A32)

VJCVT<c>.S32.F64 <Sd>, <Dm>

Converts double to signed 32-bit integer (JS semantics).

Details

Converts a 64-bit double-precision floating-point value to a signed 32-bit integer using JavaScript semantics (NaN maps to 0, out-of-range values saturate). The result is stored as a single-precision floating-point value in the destination 32-bit register. Condition flags are unaffected. This instruction requires the VFP JavaScript extension and executes in A32 (ARM) instruction set only.

Pseudocode Operation

f64_val = Dm[0:63]
if IsNaN(f64_val) then
  s32_val = 0
else if f64_val > 2147483647.0 then
  s32_val = 2147483647
else if f64_val < -2147483648.0 then
  s32_val = -2147483648
else
  s32_val = RoundTowardsZero(f64_val)
Sd[0:31] = F32(s32_val)

Example

VJCVT.S32.F64 s0, d2

Encoding

Binary Layout
cond
11101
D
11
1
001
Vd
10
11
1
1
M
0
Vm
 
Format VFP Convert
Opcode 0x0EB90BC0
Extension VFP (JS)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EB90BC0 VJCVT{<q>}.S32.F64 <Sd>, <Dm> A32 cond | 11101 | D | 11 | 1 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm
0xEEB90BC0 VJCVT{<q>}.S32.F64 <Sd>, <Dm> T32 111011101 | D | 11 | 1 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm

Description

Javascript Convert to signed fixed-point, rounding toward Zero. This instruction converts the double-precision floating-point value in the SIMD&FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. If the result is too large to be accommodated as a signed 32-bit integer, then the result is the integer modulo 232, as held in a 32-bit signed integer. This instruction can generate a floating-point exception. Depending on the settings in FPSCR, the exception results in either a flag being set or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

EncodingSpecificOperations();
CheckVFPEnabled(TRUE);
bits(64) fltval = D[m];
bits(32) intval;
bit      Z;
(intval, Z) = FPToFixedJS(fltval, FPSCR[], FALSE, 32);
FPSCR<31:28> = '0':Z:'00';
S[d] = intval;