vabd

Vector Absolute Difference

VABD<c>.<dt> <Qd>, <Qn>, <Qm>

Computes absolute difference between elements.

Details

NEON Vector Absolute Difference: computes the absolute difference between corresponding elements in Qn and Qm and stores results in Qd. The data type (dt) determined by sz specifies element width (8, 16, or 32 bits). NEON flags are not modified; no general condition flags are affected.

Pseudocode Operation

for i = 0 to num_elements(Qd, dt) - 1
  Qd[i] ← abs(Qn[i] - Qm[i])

Example

VABD.dt q0, q1, q2

Encoding

Binary Layout
1111001
U
0
D
size
Vn
Vd
0111
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2000700
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3200D00 VABD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 1 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 0 | M | 0 | Vm
0xF3200D40 VABD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 1 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm
0xFF200D00 VABD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 1 | 11110 | D | 1 | sz | Vn | Vd | 1101 | N | 0 | M | 0 | Vm
0xFF200D40 VABD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 1 | 11110 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm
0xF2000700 VABD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0111 | N | 0 | M | 0 | Vm
0xF2000740 VABD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0111 | N | 1 | M | 0 | Vm
0xEF000700 VABD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | U | 11110 | D | size | Vn | Vd | 0111 | N | 0 | M | 0 | Vm
0xEF000740 VABD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | U | 11110 | D | size | Vn | Vd | 0111 | N | 1 | M | 0 | Vm

Description

Vector Absolute Difference (integer) subtracts the elements of one vector from the corresponding elements of another vector, and places the absolute values of the results in the elements of the destination vector. Operand and result elements are all integers of the same length. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Elem[Din[n+r],e,esize];
            op2 = Elem[Din[m+r],e,esize];
            absdiff = Abs(Int(op1,unsigned) - Int(op2,unsigned));
            if long_destination then
                Elem[Q[d>>1],e,2*esize] = absdiff<2*esize-1:0>;
            else
                Elem[D[d+r],e,esize] = absdiff<esize-1:0>;