vqdmull

Vector Saturating Doubling Multiply Long

VQDMULL<c>.<dt> <Qd>, <Dn>, <Dm>

Multiplies narrow elements, doubles, and saturates into wide elements.

Details

Performs signed fixed-point saturating doubling multiply long on NEON vectors, widening narrow elements to double-width results. Each element in Dn is multiplied by the corresponding element in Dm, the result is doubled, saturated to the wider data type range, and written to the corresponding location in Qd. The NEON condition flags are not affected; saturation is indicated via the FPSCR QC bit.

Pseudocode Operation

for i = 0 to elements_in_64bit(dt) - 1 do
  product ← (Dn[i] * Dm[i]) * 2
  Qd[i] ← SignedSaturate(product, widen(dt))
FPSCR.QC ← FPSCR.QC OR (saturation occurred)

Example

VQDMULL.dt q0, d1, d2

Encoding

Binary Layout
1111001
0
1
D
size
Vn
Vd
1101
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2800D00
Extension NEON (SIMD)

Operands

  • Qd
    Dest Wide
  • Dn
    First source 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800D00 VQDMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm> A32 1111001 | 0 | 1 | D | size | Vn | Vd | 1101 | N | 0 | M | 0 | Vm
0xF2800B40 VQDMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm[x]> A32 1111001 | 0 | 1 | D | size | Vn | Vd | 1011 | N | 1 | M | 0 | Vm
0xEF800D00 VQDMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm> T32 111 | 0 | 11111 | D | size | Vn | Vd | 1101 | N | 0 | M | 0 | Vm
0xEF800B40 VQDMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm[x]> T32 111 | 0 | 11111 | D | size | Vn | Vd | 1011 | N | 1 | M | 0 | Vm

Description

Vector Saturating Doubling Multiply Long multiplies corresponding elements in two doubleword vectors, doubles the products, and places the results in a quadword vector. The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD scalars. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    integer op2;
    if scalar_form then op2 = SInt(Elem[Din[m],index,esize]);
    for e = 0 to elements-1
        if !scalar_form then op2 = SInt(Elem[Din[m],e,esize]);
        op1 = SInt(Elem[Din[n],e,esize]);
        // The following only saturates if both op1 and op2 equal -(2^(esize-1))
        (product, sat) = SignedSatQ(2*op1*op2, 2*esize);
        Elem[Q[d>>1],e,2*esize] = product;
        if sat then FPSCR.QC = '1';