svc

Supervisor Call

SVC #<imm>

Causes a Supervisor Call exception (to EL1).

Pseudocode Operation

ELR_EL1 ← PC
ESR_EL1.ISS[15:0] ← imm16
ESR_EL1.EC ← 0b010001
PSTATE.DAIF ← PSTATE.DAIF OR 0b1111
PC ← ExceptionVectorAddress(EL1, SVC)

Example

SVC #16

Encoding

Binary Layout

11010100

31:24

000

23:21

imm16

20:5

000

4:2

1:0

Format Exception

Opcode 0xD4000001

Extension System

Operands

imm
ID

Other forms of svc

svc Supervisor Call (Thumb)
svc Supervisor Call (A32)

Across architectures

System Call : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xD4000001	SVC #<imm>		A64		11010100 \| 000 \| imm16 \| 000 \| 01

Description

Supervisor Call causes an exception to be taken to EL1. On executing an SVC instruction, the PE records the exception as a Supervisor Call exception in ESR_ELx, using the EC value 0x15, and the value of the immediate argument.

Operation

AArch64.CheckForSVCTrap(imm16);
AArch64.CallSupervisor(imm16);

svc