addp

Vector Add Pairwise

ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Adds adjacent pairs of elements.

Details

Adds adjacent pairs of elements across the two source vectors element-wise, placing results in the destination. For example, with 32-bit elements, pairs (Vn[1],Vn[0]) and (Vm[1],Vm[0]) sum to (Vd[1],Vd[0]). Executes in AArch64 with NEON support; condition flags are not affected. Overflow wraps modulo 2^(element_width).

Pseudocode Operation

for i = 0 to num_pairs-1 do
  Vd[2*i] ← Vn[2*i] + Vn[2*i+1]
  Vd[2*i+1] ← Vm[2*i] + Vm[2*i+1]

Example

ADDP v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
size
1
Rm
10111
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E20BC00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5EF1B800 ADDP D<d>, <Vn>.2D A64 01 | 0 | 11110 | 11 | 11000 | 11011 | 10 | Rn | Rd
0x0E20BC00 ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | size | 1 | Rm | 10111 | 1 | Rn | Rd
0x4411A000 ADDP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01000100 | size | 010 | 0 | 0 | 1 | 101 | Pg | Zm | Zdn

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[concat, 2*e, esize];
    element2 = Elem[concat, (2*e)+1, esize];
    Elem[result, e, esize] = element1 + element2;

V[d, datasize] = result;