stz2g

Store Allocation Tag and Zero (Two Granules)

STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]

Stores Tag and zeros memory for two granules.

Details

Stores the Allocation Tag from Xt to two consecutive 16-byte memory granules and zeros both granules. The offset is scaled by 16. Useful for initializing memory with a specific tag. No condition flags are affected. AArch64-only; requires MTE extension.

Pseudocode Operation

address ← Xn + (SignExtend(imm9, 9) << 4)
tag ← GetAllocationTag(Xt)
memory[address : address + 15] ← 0 with tag set to tag
memory[address + 16 : address + 31] ← 0 with tag set to tag

Example

STZ2G Xt, [x1, #-8]

Encoding

Binary Layout
11011001
11
1
imm9
10
Xn
Xt
 
Format Load/Store
Opcode 0xD9E00800
Extension MTE (Memory Tagging)

Operands

  • Xt
    Source Tag
  • Xn
    First source / base 64-bit integer register
  • simm
    Signed immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xD9E00400 STZ2G <Xt|SP>, [<Xn|SP>], #<simm> A64 11011001 | 11 | 1 | imm9 | 01 | Xn | Xt
0xD9E00C00 STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! A64 11011001 | 11 | 1 | imm9 | 11 | Xn | Xt
0xD9E00800 STZ2G <Xt|SP>, [<Xn|SP>{, #<simm>}] A64 11011001 | 11 | 1 | imm9 | 10 | Xn | Xt

Description

Store Allocation Tags, Zeroing stores an Allocation Tag to two Tag granules of memory, zeroing the associated data locations. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag granule. The Allocation Tag is calculated from the Logical Address Tag in the source register. This instruction generates an Unchecked access.

Operation

bits(64) address;
bits(64) address2;
bits(64) data = if t == 31 then SP[] else X[t, 64];
bits(4) tag = AArch64.AllocationTagFromAddress(data);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

AccessDescriptor accdesc = CreateAccDescLDGSTG(MemOp_STORE, FALSE);

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

address2 = GenerateAddress(address, TAG_GRANULE, accdesc);

if !IsAligned(address, TAG_GRANULE) then
    AArch64.Abort(address, AlignmentFault(accdesc));

Mem[address, TAG_GRANULE, accdesc] = Zeros(TAG_GRANULE * 8);
Mem[address2, TAG_GRANULE, accdesc] = Zeros(TAG_GRANULE * 8);

AArch64.MemTag[address, accdesc] = tag;
AArch64.MemTag[address2, accdesc] = tag;

if writeback then
    if postindex then
        address = GenerateAddress(address, offset, accdesc);

    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;