Integer and Floating-Point Conversion

Convert between integer and floating-point representations.

Floating Point

Semantics

Conversion has to choose a rounding mode and a behaviour for values that do not fit. Architectures differ in whether the rounding mode is encoded in the instruction or read from a control register.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction The doubled T in CVTTSS2SI means truncate toward zero; without it the rounding mode in MXCSR applies, so the same conversion can behave differently depending on state set elsewhere.
ARM one instruction SCVTF converts signed integer to floating point, FCVTZS converts back rounding toward zero. The rounding mode is part of the mnemonic, so the instruction says what it does without reference to a control register.
RISC-V one instruction The mnemonic names both types as fcvt.<to>.<from>, so the direction is readable at a glance. Rounding mode is a three-bit instruction field that can defer to the fcsr default.
PowerISA one instruction FCFID converts a 64-bit integer to double and FCTID converts back. The integer operand lives in a floating-point register rather than a GPR, so a round trip through memory or a direct move is often needed either side.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Memory Barrier / Fence No Operation Population Count Read Cycle Counter Rotate Left Sign Extend Byte Spin-Wait Hint System Call