Logical and Arithmetic Shift

Shift a register left or right, filling with zeros or with the sign bit.

Bit Manipulation

Semantics

Left shift, logical right shift and arithmetic right shift. The differences worth knowing are whether the shift disturbs the flags, and how the shift count is masked when it exceeds the register width.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction Shifts write the flags, which constrains scheduling around a flag-consuming branch, and a shift by zero leaves them untouched, an awkward special case. The count is masked to 5 or 6 bits by the hardware.
ARM one instruction In A64 these are aliases rather than opcodes: LSL and LSR are encodings of UBFM and ASR of SBFM. The architecture provides a general bitfield move and treats shifts as special cases of it, which is why the disassembler and the encoding disagree about what instruction you wrote.
RISC-V one instruction Register and immediate forms are distinct opcodes, SLL against SLLI. No flags exist to disturb, so shifts reorder freely against everything around them.
PowerISA one instruction Separate 32-bit and 64-bit forms, SLW against SLD. SRAW is the odd one: it sets the XER carry bit to record whether any 1 bits were shifted out, which makes an arithmetic-shift division round correctly with one following instruction.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load-Acquire Load-Linked / Store-Conditional Memory Barrier / Fence No Operation Population Count Read Cycle Counter Rotate Left Sign Extend Byte Spin-Wait Hint System Call