Spin-Wait Hint

Tell the processor that the current loop is waiting rather than working.

System

Semantics

A hint with no architectural effect on results, used to yield pipeline or thread resources while polling a lock, and to avoid the pipeline flush that a memory-order violation causes on exit from a spin loop.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction PAUSE marks a spin loop so the core can de-pipeline it, and avoids the costly memory-order violation that otherwise occurs when the loop finally exits. Encoded as REP NOP, so it is harmless on processors that predate it.
ARM one instruction YIELD hints an SMT core that this thread is spinning. WFE goes further and parks the core until an event arrives, which paired with the global monitor gives a spin loop that consumes no power while waiting.
RISC-V one instruction PAUSE is a HINT encoding from Zihintpause, deliberately chosen from the reserved FENCE space so that older implementations decode it as a no-op rather than trapping. WFI waits for an interrupt and is privileged.
PowerISA an idiom The long-standing idiom is a no-op form of OR, written or 1,1,1, whose register choice sets the thread priority rather than computing anything. WAIT stops the thread until an exception or event, a stronger action than a hint.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Memory Barrier / Fence No Operation Population Count Read Cycle Counter Rotate Left Sign Extend Byte System Call