Integer Multiply
Multiply two integer registers, keeping the low half or the full double-width product.
Arithmetic
Semantics
rd = rs1 * rs2. Architectures differ in how the upper half of the product is obtained: a second instruction, an implicit register pair, or a wide destination.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | The one-operand forms write a fixed register pair (RDX:RAX) for the full 128-bit product; the modern IMUL forms take explicit registers and keep only the low half. | |
| ARM | one instruction | MUL is an alias of MADD with the addend register set to XZR, so multiply and multiply-accumulate share one encoding. | |
| RISC-V | one instruction | The M extension splits the product: MUL yields the low half and MULH the high half, so a full-width product is two instructions that a core may fuse. | |
| PowerISA | one instruction | mulld gives the low 64 bits and mullw the 32-bit form; mulhd is the separate high-half instruction. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call