Load and Store

Move a value between a register and memory.

Memory System

Semantics

rd = *(base + offset) and the reverse. The interesting difference is not the operation but the addressing modes: how much address arithmetic the instruction can absorb.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction One mnemonic for both directions; which one it is depends on which operand is memory. The addressing mode is unusually rich, base + index*scale + displacement in a single instruction, so array indexing rarely needs separate arithmetic.
ARM one instruction Separate mnemonics, with register or immediate offsets and pre- and post-indexed forms that write the computed address back to the base register. A pointer walk is therefore one instruction per step rather than two.
RISC-V one instruction Access width is in the mnemonic and the only addressing mode is base plus a 12-bit signed offset. No index register, no scaling, no writeback: address arithmetic is deliberately a separate instruction, which is the clearest expression of the ISA's minimalism.
PowerISA one instruction Width and extension are both in the mnemonic, so LWZ is load word and zero-extend. Indexed forms such as LWZX take two registers, and update forms such as LWZU write the address back, giving PowerISA both of the modes RISC-V leaves out.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call