RV64I Instructions
12 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| ADDIW | ADDIW rd, rs1, imm | I-Type | Adds a 12-bit immediate to a register (32-bit arithmetic) and sign-extends to 64 bits. |
| ADDW | ADDW rd, rs1, rs2 | R-Type | Adds two 32-bit registers and sign-extends the result to 64 bits. |
| LD | LD rd, offset(rs1) | I-Type | Loads a 64-bit doubleword from memory. |
| LWU | LWU rd, offset(rs1) | I-Type | Loads a 32-bit word from memory and zero-extends it to 64 bits. |
| SD | SD rs2, offset(rs1) | S-Type | Stores a 64-bit doubleword to memory. |
| SLLIW | SLLIW rd, rs1, shamt | I-Type (Shift) | Shifts the lower 32 bits of rs1 left by a constant, sign-extending the result. |
| SLLW | SLLW rd, rs1, rs2 | R-Type | Performs a 32-bit logical left shift on rs1 by the amount in rs2 (lower 5 bits), sign-extending the result. |
| SRAIW | SRAIW rd, rs1, shamt | I-Type (Shift) | Arithmetically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result. |
| SRAW | SRAW rd, rs1, rs2 | R-Type | Performs a 32-bit arithmetic right shift on rs1, sign-extending the result. |
| SRLIW | SRLIW rd, rs1, shamt | I-Type (Shift) | Logically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result. |
| SRLW | SRLW rd, rs1, rs2 | R-Type | Performs a 32-bit logical right shift on rs1 by the amount in rs2, sign-extending the result. |
| SUBW | SUBW rd, rs1, rs2 | R-Type | Subtracts the lower 32 bits of rs2 from rs1 and sign-extends the result to 64 bits. |